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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Ddavinci_emac.txt12 - ti,davinci-ctrl-ram-offset: offset to control module ram
13 - ti,davinci-ctrl-ram-size: size of control module ram
24 - ti,davinci-no-bd-ram: boolean, does EMAC have BD RAM?
35 ti,davinci-ctrl-ram-offset = <0>;
36 ti,davinci-ctrl-ram-size = <0x2000>;
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dbosch,m_can.yaml24 - description: message RAM
55 Message RAM configuration data.
56 Multiple M_CAN instances can share the same Message RAM
58 in Message RAM is also configurable, so this property is
59 telling driver how the shared or private Message RAM are
64 The 'offset' is an address offset of the Message RAM where
66 0x0 if you're using a private Message RAM. The remain cells
78 Please refer to 2.4.1 Message RAM Configuration in Bosch
82 - description: The 'offset' is an address offset of the Message RAM where
84 you're using a private Message RAM.
H A Dti_hecc.txt9 - reg: addresses and lengths of the register spaces for 'hecc', 'hecc-ram'
11 - reg-names :"hecc", "hecc-ram", "mbx"
29 reg-names = "hecc", "hecc-ram", "mbx";
/freebsd/sys/dev/ixl/
H A Di40e_nvm.c44 * We are accessing FLASH always through the Shadow RAM.
176 * Polls the SRCTL Shadow RAM register done bit.
200 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
202 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
203 * @data: word read from the Shadow RAM
205 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
217 "NVM read error: Offset %d beyond Shadow RAM limit %d\n", in i40e_read_nvm_word_srctl()
242 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n", in i40e_read_nvm_word_srctl()
250 * i40e_read_nvm_aq - Read Shadow RAM.
255 * @data: buffer with words to write to the Shadow RAM
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra20-emc.txt9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
56 Embedded Memory Controller ram-code table
58 If the emc node has the nvidia,use-ram-code property present, then the
60 apply for which ram-code settings.
62 If the emc node lacks the nvidia,use-ram-code property, this level is omitted
68 - nvidia,ram-code : the binary representation of the ram-code board strappings
90 on a 2-pin "ram code" bootstrap setting on the board. The values of
H A Dbaikal,bt1-l2-ctl.yaml16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
29 description: Cycles of latency for Way-select RAM accesses
36 description: Cycles of latency for Tag RAM accesses
43 description: Cycles of latency for Data RAM accesses
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a73/
H A Dcache.json54 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
57 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
60 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
63 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
66 "PublicDescription": "Number of ways read in the instruction BTAC RAM",
69 "BriefDescription": "Number of ways read in the instruction BTAC RAM"
/freebsd/sys/dev/ice/
H A Dice_nvm.c44 * @read_shadow_ram: tell if this is a shadow RAM read
86 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
89 * breaks read requests across Shadow RAM sectors and ensures that no single
108 /* Verify the length of the read if this is for the Shadow RAM */ in ice_read_flat_nvm()
110 ice_debug(hw, ICE_DBG_NVM, "NVM error: requested data is beyond Shadow RAM limit\n"); in ice_read_flat_nvm()
118 * Additionally, a read from the Shadow RAM may not cross over in ice_read_flat_nvm()
298 * ice_check_sr_access_params - verify params for Shadow RAM R/W operations
329 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
331 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
332 * @data: word read from the Shadow RAM
[all...]
/freebsd/usr.sbin/bhyve/amd64/
H A De820.c79 return ("RAM"); in e820_get_type_name()
219 * [ 0x1000, 0x4000] RAM <-- element in e820_add_entry()
233 * [ 0x1000, 0x4000] RAM <-- element in e820_add_entry()
236 * [ 0x2000, 0x4000] RAM <-- element in e820_add_entry()
247 * [ 0x1000, 0x4000] RAM <-- element in e820_add_entry()
249 * [ 0x1000, 0x3000] RAM <-- element in e820_add_entry()
261 * [ 0x1000, 0x4000] RAM <-- element in e820_add_entry()
263 * [ 0x1000, 0x2000] RAM in e820_add_entry()
265 * [ 0x3000, 0x4000] RAM <-- element in e820_add_entry()
338 * [ 0x1000, 0x4000] RAM in e820_add_memory_hole()
[all …]
H A Datkbdc.c129 uint8_t ram[RAMSZ]; /* byte0 = controller config */ member
145 if ((sc->ram[0] & KBD_ENABLE_KBD_INT) != 0) { in atkbdc_assert_kbd_intr()
154 if ((sc->ram[0] & KBD_ENABLE_AUX_INT) != 0) { in atkbdc_assert_aux_intr()
220 if (sc->ram[0] & KBD_TRANSLATION) { in atkbdc_kbd_read()
240 if (((sc->ram[0] & KBD_DISABLE_AUX_PORT) || in atkbdc_kbd_read()
342 sc->ram[0] = *eax; in atkbdc_data_handler()
343 if (sc->ram[0] & KBD_SYS_FLAG_BIT) in atkbdc_data_handler()
364 /* write to particular RAM byte */ in atkbdc_data_handler()
369 sc->ram[byten] = *eax & 0xff; in atkbdc_data_handler()
421 sc->ctrlbyte = CTRL_CMD_FLAG | sc->ram[0]; in atkbdc_sts_ctl_handler()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dkeystone-navigator-qmss.txt6 processors(PDSP), linking RAM, descriptor pools and infrastructure
12 Linking RAM registers are used to link the descriptors which are stored in
13 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
14 The QMSS driver manages the PDSP setups, linking RAM regions,
24 - linkram0 : <address size> for internal link ram, where size is the total
25 link ram entries.
26 - linkram1 : <address size> for external link ram, where size is the total
27 external link ram entries. If the address is specified as "0"
38 - Queue status RAM.
109 - PDSP internal RAM region.
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/
H A Dcache.json111 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
114 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
117 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
120 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
123 "PublicDescription": "Number of ways read in the instruction BTAC RAM",
126 "BriefDescription": "Number of ways read in the instruction BTAC RAM"
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,rpm-master-stats.yaml33 qcom,rpm-msg-ram:
35 description: Phandle to an RPM MSG RAM slice containing the master stats
44 The name of the RPM Master which owns the MSG RAM slice where this
51 - qcom,rpm-msg-ram
60 qcom,rpm-msg-ram = <&apss_master_stats>,
H A Dqcom,smem.txt17 - qcom,rpm-msg-ram:
30 at 0xfa00000 and the RPM message ram at 0xfc428000:
47 qcom,rpm-msg-ram = <&rpm_msg_ram>;
54 compatible = "qcom,rpm-msg-ram";
H A Dqcom,aoss-qmp.txt6 SoC has it's own block of message RAM and IRQ for communication with the AOSS.
7 The protocol used to communicate in the message RAM is known as Qualcomm
29 Definition: the base address and size of the message RAM for this
69 The following example represents the AOSS side-channel message RAM and the
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dste-db8500.dtsi21 ram@6000000 {
27 ram@6f00000 {
33 ram@7000000 {
47 ram@17f00000 {
H A Dste-db8520.dtsi21 ram@6000000 {
27 ram@6f00000 {
33 ram@7000000 {
47 ram@17f00000 {
/freebsd/sys/sys/
H A Dphysmem.h37 * Routines to help configure physical ram.
39 * Multiple regions of contiguous physical ram can be added (in any order).
41 * Multiple regions of physical ram that should be excluded from crash dumps, or
45 * remainining non-excluded physical ram for use by other parts of the kernel,
48 * that communicate physical ram configuration to other parts of the kernel.
/freebsd/sys/arm64/coresight/
H A Dcoresight_tmc.h34 #define TMC_RSZ 0x004 /* RAM Size Register */
42 #define TMC_RRD 0x010 /* RAM Read Data Register */
43 #define TMC_RRP 0x014 /* RAM Read Pointer Register */
44 #define TMC_RWP 0x018 /* RAM Write Pointer Register */
48 #define TMC_RWD 0x024 /* RAM Write Data Register */
56 #define TMC_RRPHI 0x038 /* RAM Read Pointer High Register */
57 #define TMC_RWPHI 0x03C /* RAM Write Pointer High Register */
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dbaikal,bt1-l2-ctl.yaml16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
29 description: Cycles of latency for Way-select RAM accesses
36 description: Cycles of latency for Tag RAM accesses
43 description: Cycles of latency for Data RAM accesses
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dfsl,imx-sdma.yaml58 fsl,sdma-ram-script-name:
60 description: Should contain the full path of SDMA RAM scripts firmware.
131 description: The phandle to the On-chip RAM (OCRAM) node.
137 - fsl,sdma-ram-script-name
148 fsl,sdma-ram-script-name = "sdma-imx51.bin";
/freebsd/sys/dev/e1000/
H A De1000_i210.c80 * e1000_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
82 * @offset: offset of word in the Shadow Ram to read
84 * @data: word read from the Shadow Ram
86 * Reads a 16 bit word from the Shadow Ram using the EERD register.
119 * e1000_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
121 * @offset: offset within the Shadow RAM to be written to
123 * @data: 16 bit word(s) to be written to the Shadow RAM
125 * Writes data to Shadow RAM at offset using EEWR register.
128 * data will not be committed to FLASH and also Shadow RAM will most likely
131 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
[all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dqcom,glink-rpm-edge.yaml38 qcom,rpm-msg-ram:
41 RPM message memory resource (compatible: qcom,rpm-msg-ram).
78 - qcom,rpm-msg-ram
90 qcom,rpm-msg-ram = <&rpm_msg_ram>;
/freebsd/sys/dev/igc/
H A Digc_i225.c435 /* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register
437 * @offset: offset of word in the Shadow Ram to read
439 * @data: word read from the Shadow Ram
441 * Reads a 16 bit word from the Shadow Ram using the EERD register.
474 /* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR
476 * @offset: offset within the Shadow RAM to be written to
478 * @data: 16 bit word(s) to be written to the Shadow RAM
480 * Writes data to Shadow RAM at offset using EEWR register.
483 * data will not be committed to FLASH and also Shadow RAM will most likely
486 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
[all …]
/freebsd/sys/contrib/openzfs/.github/workflows/scripts/
H A Dqemu-5-setup.sh27 RAM=6
31 RAM=8
81 --memory $((1024*RAM)) \
110 echo "Waiting for vm's to come up... (${VMs}x CPU=$CPU RAM=$RAM)"

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