Searched full:qusb2phy_intr_ctrl (Results 1 – 3 of 3) sorted by relevance
53 /* QUSB2PHY_INTR_CTRL register bits */135 QUSB2PHY_INTR_CTRL, enumerator177 [QUSB2PHY_INTR_CTRL] = 0xBC,190 [QUSB2PHY_INTR_CTRL] = 0xbc,219 [QUSB2PHY_INTR_CTRL] = 0x22c,261 [QUSB2PHY_INTR_CTRL] = 0x230,669 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_suspend()730 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_resume()
132 by the QUSB2PHY_INTR_CTRL register. The required DPSE/133 DMSE configuration is done in QUSB2PHY_INTR_CTRL register
127 by the QUSB2PHY_INTR_CTRL register. The required DPSE/128 DMSE configuration is done in QUSB2PHY_INTR_CTRL register