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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-fm-tx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _fm-tx-controls:
16 .. _fm-tx-control-id:
28 step are driver-specific.
35 to 31 pre-defined programme types.
53 programme-related information or any other text. In these cases,
104 receiver-generated distortion and prevent overmodulation.
108 microseconds. Step and range are driver-specific.
112 are driver-specific.
122 range and step are driver-specific.
[all …]
H A Dext-ctrls-fm-rx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _fm-rx-controls:
14 .. _fm-rx-control-id:
28 Gets RDS Programme Type field. This encodes up to 31 pre-defined
46 wishes to transmit longer PS names, programme-related information or
69 Configures the de-emphasis value for reception. A de-emphasis filter
73 values for de-emphasis. They are:
75 .. flat-table::
76 :header-rows: 0
77 :stub-columns: 0
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
9 #include <dt-bindings/phy/phy.h>
114 /* u2phy-grf */
118 /* usb-grf */
122 /* usbdpphy-grf */
128 /* vo-grf */
178 bool hs; /* flag for high-speed */
205 /* voltage swing 0, pre-emphasis 0->3 */
213 /* voltage swing 1, pre-emphasis 0->2 */
[all …]
H A Dphy-rockchip-samsung-hdptx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024-2026 Collabora Ltd.
6 * Author: Algea Cao <algea.cao@rock-chips.com>
11 #include <linux/clk-provider.h>
804 /* Keep Inter-Pair Skew in the limits */
828 /* Keep Inter-Pair Skew in the limits */
836 /* voltage swing 0, pre-emphasis 0->3 */
844 /* voltage swing 1, pre-emphasis 0->2 */
851 /* voltage swing 2, pre-emphasis 0->1 */
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dapm,xgene-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/apm,xgene-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene 15Gbps Multi-purpose PHY
10 - Khuong Dinh <khuong@os.amperecomputing.com>
13 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
19 - const: apm,xgene-phy
24 '#phy-cells':
32 apm,tx-eye-tuning:
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H A Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Wesley Cheng <quic_wcheng@quicinc.com>
19 - items:
20 - enum:
21 - qcom,ipq5424-qusb2-phy
22 - qcom,ipq6018-qusb2-phy
23 - qcom,ipq8074-qusb2-phy
[all …]
H A Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy(@[0-9a-f]+)?$"
[all …]
H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
48 vdda1v1-supply:
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/linux/include/linux/phy/
H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
52 * @pre:
54 * Pre-emphasis levels, as specified by DisplayPort specification, to be
59 unsigned int pre[4]; member
64 * Flag indicating, whether or not to enable spread-spectrum clocking.
91 * and pre-emphasis to requested values. Only lanes specified
/linux/include/sound/
H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
[all …]
H A Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
60 /* Q-subcode frame */
62 /* Q-subcode zero */
64 /* Q-subcode absolute minute */
66 /* Q-subcode absolute second */
[all …]
H A Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
40 #define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */
41 #define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_fdi_regs.h1 /* SPDX-License-Identifier: MIT */
48 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
50 /* SNB A-stepping */
55 /* SNB B-stepping */
63 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
80 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-snps-femto-v2.c1 // SPDX-License-Identifier: GPL-2.0
82 "vdda-pll", "vdda33", "vdda18",
110 * struct qcom_snps_hsphy - snps hs phy attributes
143 struct device *dev = hsphy->dev; in qcom_snps_hsphy_clk_init()
145 hsphy->num_clks = 2; in qcom_snps_hsphy_clk_init()
146 hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); in qcom_snps_hsphy_clk_init()
147 if (!hsphy->clks) in qcom_snps_hsphy_clk_init()
148 return -ENOMEM; in qcom_snps_hsphy_clk_init()
154 hsphy->clks[0].id = "cfg_ahb"; in qcom_snps_hsphy_clk_init()
155 hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb"); in qcom_snps_hsphy_clk_init()
[all …]
H A Dphy-qcom-qusb2.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
307 /* true if PHY default clk scheme is single-ended */
408 "vdd", "vdda-pll", "vdda-phy-dpdm",
413 /* struct override_param - structure holding qusb2 v2 phy overriding param
422 /*struct override_params - structure holding qusb2 v2 phy overriding params
425 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
[all …]
/linux/drivers/phy/lantiq/
H A Dphy-lantiq-rcu-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
21 /* Transmitter HS Pre-Emphasis Enable */
69 .compatible = "lantiq,ase-usb2-phy",
73 .compatible = "lantiq,danube-usb2-phy",
77 .compatible = "lantiq,xrx100-usb2-phy",
81 .compatible = "lantiq,xrx200-usb2-phy",
85 .compatible = "lantiq,xrx300-usb2-phy",
96 if (priv->reg_bits->have_ana_cfg) { in ltq_rcu_usb2_phy_init()
97 regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset, in ltq_rcu_usb2_phy_init()
[all …]
/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
198 * struct xpsgtr_phy - representation of a lane
219 * struct xpsgtr_dev - representation of a ZynMP GT device
271 return readl(gtr_dev->serdes + reg); in xpsgtr_read()
276 writel(value, gtr_dev->serdes + reg); in xpsgtr_write()
[all …]
/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
H A Dphy-snps-eusb2.c1 // SPDX-License-Identifier: GPL-2.0
183 phy->mode = mode; in snps_eusb2_hsphy_set_mode()
185 return phy_set_mode_ext(phy->repeater, mode, submode); in snps_eusb2_hsphy_set_mode()
204 /* default parameters: tx pre-emphasis */ in qcom_eusb2_default_parameters()
205 snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_9, in qcom_eusb2_default_parameters()
210 snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_9, in qcom_eusb2_default_parameters()
215 snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_9, in qcom_eusb2_default_parameters()
220 snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_8, in qcom_eusb2_default_parameters()
225 snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_8, in qcom_eusb2_default_parameters()
248 unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); in exynos_eusb2_ref_clk_init()
[all …]
/linux/drivers/ufs/core/
H A Dufs-txeq.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "ufshcd-priv.h"
37 MODULE_PARM_DESC(adaptive_txeq_gear, "For HS-Gear[n] and above, adaptive txeq shall be used");
41 …use_txeq_presets, "Use only the 8 TX Equalization Presets (pre-defined Pre-Shoot & De-Emphasis com…
43 static bool txeq_presets_selected[UFS_TX_EQ_PRESET_MAX] = {[0 ... (UFS_TX_EQ_PRESET_MAX - 1)] = 1};
70 * ufs_tx_eq_preset - Table of minimum required list of presets.
72 * A HS-G6 capable M-TX shall support the presets defined in M-PHY v6.0 spec.
73 * Preset Pre-Shoot(dB) De-Emphasis(dB)
98 * pa_peer_rx_adapt_initial - Table of UniPro PA_PeerRxHSGnAdaptInitial
102 * attribute IDs. Entries for Gears 1-3 are 0 (unsupported).
[all …]
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_link.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
58 if (link->revision < 0x11) in msm_dp_aux_link_power_up()
85 if (link->revision < 0x11) in msm_dp_aux_link_power_down()
109 if (drm_dp_dpcd_readb(link->aux, addr, &data) < 0) { in msm_dp_link_get_period()
111 ret = -EINVAL; in msm_dp_link_get_period()
115 /* Period - Bits 3:0 */ in msm_dp_link_get_period()
119 ret = -EINVAL; in msm_dp_link_get_period()
131 struct msm_dp_link_test_audio *req = &link->msm_dp_link.test_audio; in msm_dp_link_parse_audio_channel_period()
[all …]
/linux/drivers/scsi/bfa/
H A Dbfa_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */
102 * All numerical fields are in big-endian format.
125 BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if persists,
129 BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */
132 BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */
148 BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
[all …]
/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
306 /* Exynos9 - GS101 */
440 for (; (tune)->region != PTR_INVALID; ++(tune))
494 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
502 * @hs_phy: pointer to non-Samsung IP high-speed phy controller
510 * @orientation: TypeC connector orientation - normal or flipped
540 phys[(inst)->index]); in to_usbdrd_phy()
577 return -EINVAL; in exynos5_rate_to_clk()
588 if (!inst->reg_pmu) in exynos5_usbdrd_phy_isol()
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