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/linux/drivers/mtd/nand/
H A Decc.c18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
65 * [pipelined ECC engine]
66 * - pipelined + prepare + raw + read: disable the controller's ECC engine if
68 * - pipelined + finish + raw + read: do nothing
69 * - pipelined + prepare + raw + write: disable the controller's ECC engine if
71 * - pipelined + finish + raw + write: do nothing
72 * - pipelined + prepare + ecc + read: enable the controller's ECC engine if
74 * - pipelined + finish + ecc + read: check the status, report any
76 * - pipelined + prepare + ecc + write: enable the controller's ECC engine if
78 * - pipelined + finish + ecc + write: do nothing
[all …]
H A Decc-mxic.c391 dev_info(dev, "Macronix ECC engine in pipelined/mapping mode\n"); in mxic_ecc_init_ctx_pipelined()
667 /* Pipelined ECC engine helpers */
793 * Only the external ECC engine is exported as the pipelined is SoC specific, so
836 * In external mode, the device is the ECC engine. In pipelined mode, in mxic_ecc_probe()
/linux/Documentation/devicetree/bindings/mtd/
H A Dmxicy,nand-ecc-engine.yaml56 /* Pipelined configuration */
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_ggtt_fencing.c47 #define pipelined 0 macro
91 if (!pipelined) { in i965_write_fence_reg()
138 if (!pipelined) { in i915_write_fence_reg()
163 if (!pipelined) { in i830_write_fence_reg()
H A Dgen6_engine_cs.c23 * produced by non-pipelined state commands), software needs to first
/linux/Documentation/gpu/
H A Ddrm-vm-bind-async.rst121 deeply pipelined behind other VM_BIND operations and workloads
140 buffers. The workload execution can then easily be pipelined behind
/linux/arch/mips/sgi-ip22/
H A Dip22-gio.c279 * If GIO is pipelined (which can't be disabled in ip22_gio_id()
290 * a pipelined bus, but a real card which in ip22_gio_id()
H A Dip22-mc.c161 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */ in sgimc_init()
/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mtk-snfi.yaml17 in single, dual or quad IO mode with pipelined ECC encoding/decoding
/linux/arch/m68k/include/asm/
H A Dmcfwdebug.h80 #define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt48 synchronous pipelined devices, where the address
/linux/drivers/isdn/mISDN/
H A Ddsp_pipeline.c3 * dsp_pipeline.c: pipelined audio processing
/linux/arch/mips/include/asm/sgi/
H A Dmc.h85 #define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */
/linux/include/linux/hsi/
H A Dhsi.h32 HSI_FLOW_PIPE, /* Pipelined flow */
/linux/arch/powerpc/kernel/
H A Dl2cr_6xx.S59 - L2RAM set to pipelined synchronous late-write
/linux/include/drm/ttm/
H A Dttm_resource.h183 * @move: The fence of the last pipelined move operation.
/linux/arch/powerpc/platforms/chrp/
H A Dsetup.c83 "Pipelined Synchronous"
/linux/drivers/gpu/drm/kmb/
H A Dkmb_drv.c240 * then disable DMA pipelined AXI read in handle_lcd_irq()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_domain.c420 * an uninterruptible phase (modesetting) and allows any flushes to be pipelined
/linux/drivers/gpu/drm/xe/
H A Dxe_lrc.c1610 * except that 3DSTATE_DRAWING_RECTANGLE (non-pipelined) has in xe_lrc_emit_hwe_state_instructions()
1611 * been replaced by 3DSTATE_DRAWING_RECTANGLE_FAST (pipelined). in xe_lrc_emit_hwe_state_instructions()
/linux/Documentation/arch/sparc/oradax/
H A Ddax-hv-api.txt1051 …In the case of pipelined CCBs, a page overflow error will be triggered if the output from the pipe…
1393 36.3.3.1. Interactions with Pipelined CCBs
/linux/drivers/gpu/drm/ttm/
H A Dttm_bo_util.c641 * @pipeline: evictions are to be pipelined.
/linux/arch/powerpc/include/asm/
H A Dreg.h690 #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
691 #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
/linux/drivers/net/ethernet/sfc/falcon/
H A Drx.c53 * to allow pipelined receives.
/linux/drivers/net/ethernet/sfc/siena/
H A Drx_common.c30 * to allow pipelined receives.

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