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/linux/Documentation/devicetree/bindings/pwm/
H A Dmicrochip,corepwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
37 microchip,sync-update-mask:
[all …]
H A Dimg-pwm.txt1 *Imagination Technologies PWM DAC driver
4 - compatible: Should be "img,pistachio-pwm"
5 - reg: Should contain physical base address and length of pwm registers.
6 - clocks: Must contain an entry for each entry in clock-names.
7 See ../clock/clock-bindings.txt for details.
8 - clock-names: Must include the following entries.
9 - pwm: PWM operating clock.
10 - sys: PWM system interface clock.
11 - #pwm-cells: Should be 2. See pwm.yaml in this directory for the
13 - img,cr-periph: Must contain a phandle to the peripheral control
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
[all …]
H A Dstm32h743.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32h7-clks.h>
45 #include <dt-bindings/mfd/stm32h7-rcc.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
[all …]
H A Dstm32mp157c-emstamp-argon.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include "stm32mp15-pinctrl.dtsi"
10 #include "stm32mp15xxac-pinctrl.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/mfd/st,stpmic1.h>
23 stdout-path = "serial0:115200n8";
31 reserved-memory {
32 #address-cells = <1>;
33 #size-cells = <1>;
37 compatible = "shared-dma-pool";
[all …]
H A Dstihxxx-b2120.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/stih407-clks.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/media/c8sectpfe.h>
11 compatible = "gpio-leds";
12 led-red {
15 linux,default-trigger = "heartbeat";
17 led-green {
19 default-state = "off";
24 compatible = "simple-audio-card";
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dstarfive,jh7110-pwmdac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/starfive,jh7110-pwmdac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PWM-DAC Controller
10 The PWM-DAC Controller uses PWM square wave generators plus RC filters to
11 form a DAC for audio play in StarFive JH7110 SoC. This audio play controller
16 - Hal Feng <hal.feng@starfivetech.com>
19 - $ref: dai-common.yaml#
23 const: starfive,jh7110-pwmdac
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H A Daxentia,tse850-pcm5142.txt1 Devicetree bindings for the Axentia TSE-850 audio complex
4 - compatible: "axentia,tse850-pcm5142"
5 - axentia,cpu-dai: The phandle of the cpu dai.
6 - axentia,audio-codec: The phandle of the PCM5142 codec.
7 - axentia,add-gpios: gpio specifier that controls the mixer.
8 - axentia,loop1-gpios: gpio specifier that controls loop relays on channel 1.
9 - axentia,loop2-gpios: gpio specifier that controls loop relays on channel 2.
10 - axentia,ana-supply: Regulator that supplies the output amplifier. Must
11 support voltages in the 2V - 20V range, in 1V steps.
16 IN1 +---o +------------+ o---+ OUT1
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/linux/Documentation/hwmon/
H A Dadm1026.rst16 - Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
17 - Justin Thiessen <jthiessen@penguincomputing.com>
20 -----------------
23 List of GPIO pins (0-16) to program as inputs
26 List of GPIO pins (0-16) to program as outputs
29 List of GPIO pins (0-16) to program as inverted
32 List of GPIO pins (0-16) to program as normal/non-inverted
35 List of GPIO pins (0-7) to program as fan tachs
39 -----------
45 16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit),
[all …]
/linux/sound/soc/starfive/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 tristate "JH7110 PWM-DAC device driver"
17 PWM-DAC driver.
H A Djh7110_pwmdac.c1 // SPDX-License-Identifier: GPL-2.0
3 * jh7110_pwmdac.c -- StarFive JH7110 PWM-DAC driver
5 * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
115 value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); in jh7110_pwmdac_set_enable()
121 jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); in jh7110_pwmdac_set_enable()
128 value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); in jh7110_pwmdac_set_shift()
129 if (dev->cfg.shift == PWMDAC_SHIFT_8) in jh7110_pwmdac_set_shift()
131 else if (dev->cfg.shift == PWMDAC_SHIFT_10) in jh7110_pwmdac_set_shift()
134 jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); in jh7110_pwmdac_set_shift()
141 value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); in jh7110_pwmdac_set_duty_cycle()
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-tse850-3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board
9 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
11 #include "at91-linea.dtsi"
14 model = "Axentia TSE-850 3.0";
19 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <16000000>;
23 clock-output-names = "sck";
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
[all …]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvfxxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "vf610-pinfunc.h"
6 #include <dt-bindings/clock/vf610-clock.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
[all …]
/linux/drivers/hwmon/
H A Dmax6650.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * max6650.c - Part of lm_sensors, Linux kernel modules for hardware
18 * http://pdfserv.maxim-ic.com/en/ds/MAX6650-MAX6651.pdf
27 #include <linux/hwmon-sysfs.h>
91 /* Minimum and maximum values of the FAN-RPM */
114 u8 dac; member
140 static int dac_to_pwm(int dac, bool v12) in dac_to_pwm() argument
143 * Useful range for dac is 0-180 for 12V fans and 0-76 for 5V fans. in dac_to_pwm()
144 * Lower DAC values mean higher speeds. in dac_to_pwm()
146 return clamp_val(255 - (255 * dac) / DAC_LIMIT(v12), 0, 255); in dac_to_pwm()
[all …]
/linux/arch/mips/boot/dts/img/
H A Dpistachio_marduk.dts1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
14 compatible = "img,pistachio-marduk", "img,pistachio";
26 stdout-path = "serial1:115200";
34 reg_1v8: fixed-regulator {
35 compatible = "regulator-fixed";
36 regulator-name = "aux_adc_vref";
37 regulator-min-microvolt = <1800000>;
38 regulator-max-microvolt = <1800000>;
39 regulator-boot-on;
[all …]
H A Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-pinetab.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "sun50i-a64.dtsi"
10 #include "sun50i-a64-cpu-opp.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pwm/pwm.h>
18 compatible = "pine64,pinetab", "allwinner,sun50i-a64";
19 chassis-type = "tablet";
27 compatible = "pwm-backlight";
[all …]
/linux/sound/soc/codecs/
H A Dab8500-codec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
8 * for ST-Ericsson.
14 * for ST-Ericsson.
29 #include <linux/mfd/abx500/ab8500-sysctrl.h>
30 #include <linux/mfd/abx500/ab8500-codec.h>
39 #include <sound/soc-dapm.h>
42 #include "ab8500-codec.h"
56 /* Nr of FIR/IIR-coeff banks in ANC-block */
114 /* Private data for AB8500 device-driver */
[all …]
H A Dwm5100-tables.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm5100-tables.c -- WM5100 ALSA SoC Audio driver data
5 * Copyright 2011-2 Wolfson Microelectronics plc
815 { 0x0000, 0x0000 }, /* R0 - software reset */
816 { 0x0001, 0x0000 }, /* R1 - Device Revision */
817 { 0x0010, 0x0801 }, /* R16 - Ctrl IF 1 */
818 { 0x0020, 0x0000 }, /* R32 - Tone Generator 1 */
819 { 0x0030, 0x0000 }, /* R48 - PWM Drive 1 */
820 { 0x0031, 0x0100 }, /* R49 - PWM Drive 2 */
821 { 0x0032, 0x0100 }, /* R50 - PWM Drive 3 */
[all …]
/linux/drivers/pwm/
H A Dpwm-img.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2015, Imagination Technologies
7 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
19 #include <linux/pwm.h>
23 /* PWM registers */
43 * PWM period is specified with a timebase register,
44 * in number of step periods. The PWM duty cycle is also
49 * Imposing a minimum timebase, will impose a maximum PWM frequency.
81 writel(val, imgchip->base + reg); in img_pwm_writel()
86 return readl(imgchip->base + reg); in img_pwm_readl()
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-controller.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-controller-pxa303", "marvell,pxa300";
11 reg_vbatt: regulator-vbatt {
12 compatible = "regulator-fixed";
13 regulator-name = "vbatt-fixed-supply";
14 regulator-min-microvolt = <3700000>;
15 regulator-max-microvolt = <3700000>;
16 regulator-always-on;
[all …]
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc18xx.dtsi9 * Released under the terms of 3-clause BSD License
14 #include "../../armv7-m.dtsi"
16 #include "dt-bindings/clock/lpc18xx-cgu.h"
17 #include "dt-bindings/clock/lpc18xx-ccu.h"
23 #address-cells = <1>;
24 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-m3";
40 compatible = "fixed-clock";
[all …]
/linux/Documentation/devicetree/bindings/reset/
H A Dnxp,lpc1850-rgu.txt8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
39 38 Motor control PWM (MCPWM)
43 42 DAC
56 56 ARM Cortex-M0 application core (LPC4370 only)
59 60 ADCHS (12-bit ADC) (LPC4370 only)
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl_spear.txt4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
[all …]

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