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/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dspectrum_port_range.c26 const struct mlxsw_sp_port_range_reg *prr) in mlxsw_sp_port_range_reg_configure() argument
33 mlxsw_reg_pprr_pack(pprr_pl, prr->index); in mlxsw_sp_port_range_reg_configure()
36 mlxsw_reg_pprr_src_set(pprr_pl, prr->range.source); in mlxsw_sp_port_range_reg_configure()
37 mlxsw_reg_pprr_dst_set(pprr_pl, !prr->range.source); in mlxsw_sp_port_range_reg_configure()
40 mlxsw_reg_pprr_port_range_min_set(pprr_pl, prr->range.min); in mlxsw_sp_port_range_reg_configure()
41 mlxsw_reg_pprr_port_range_max_set(pprr_pl, prr->range.max); in mlxsw_sp_port_range_reg_configure()
52 struct mlxsw_sp_port_range_reg *prr; in mlxsw_sp_port_range_reg_create() local
55 prr = kzalloc(sizeof(*prr), GFP_KERNEL); in mlxsw_sp_port_range_reg_create()
56 if (!prr) in mlxsw_sp_port_range_reg_create()
59 prr->range = *range; in mlxsw_sp_port_range_reg_create()
[all …]
/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml44 Partial Reconfiguration Region (PRR)
46 * A PRR is a specific section of an FPGA reserved for reconfiguration.
47 * A base (or static) FPGA image may create a set of PRR's that later may
49 * The size and specific location of each PRR is fixed.
50 * The connections at the edge of each PRR are fixed. The image that is loaded
51 into a PRR must fit and must use a subset of the region's connections.
57 * An FPGA image that is designed to be loaded into a PRR. There may be
58 any number of personas designed to fit into a PRR, but only one at a time
106 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
155 base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
[all …]
/linux/Documentation/devicetree/bindings/hwinfo/
H A Drenesas,prr.yaml4 $id: http://devicetree.org/schemas/hwinfo/renesas,prr.yaml#
21 - renesas,prr
34 prr: chipid@ff000044 {
35 compatible = "renesas,prr";
/linux/arch/sh/kernel/cpu/sh4/
H A Dprobe.c17 unsigned long pvr, prr, cvr; in cpu_probe() local
29 prr = (__raw_readl(CCN_PRR) >> 4) & 0xff; in cpu_probe()
106 if (prr == 0x61) in cpu_probe()
108 else if (prr == 0xa1) in cpu_probe()
129 switch (prr) { in cpu_probe()
145 switch (prr) { in cpu_probe()
180 switch (prr) { in cpu_probe()
/linux/drivers/soc/renesas/
H A Drenesas-soc.c18 u32 reg; /* CCCR or PRR, if not in DT */
23 .reg = 0xff000044, /* PRR (Product Register) */
28 .reg = 0xff000044, /* PRR (Product Register) */
33 .reg = 0xfff00044, /* PRR (Product Register) */
63 .reg = 0xff000044, /* PRR (Product Register) */
68 .reg = 0xfff00044, /* PRR (Product Register) */
452 { .compatible = "renesas,prr", .data = &id_prr },
485 /* Try hardcoded CCCR/PRR fallback */ in renesas_soc_init()
/linux/include/linux/
H A Dadreno-smmu-priv.h54 * Region (PRR) bit in the ACTLR register.
56 * the physical address of PRR page passed from GPU
/linux/Documentation/spi/
H A Dbutterfly.rst43 (a) flash new firmware that disables SPI (set PRR.2, and disable pullups
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a78000.dtsi681 prr: chipid@189e0044 { label
682 compatible = "renesas,prr";
H A Dr8a77970.dtsi1212 prr: chipid@fff00044 { label
1213 compatible = "renesas,prr";
H A Dr8a779f0.dtsi1300 prr: chipid@fff00044 { label
1301 compatible = "renesas,prr";
H A Dr8a77995.dtsi1464 prr: chipid@fff00044 { label
1465 compatible = "renesas,prr";
H A Dr8a77980.dtsi1585 prr: chipid@fff00044 { label
1586 compatible = "renesas,prr";
H A Dr8a779h0.dtsi2186 prr: chipid@fff00044 { label
2187 compatible = "renesas,prr";
/linux/drivers/gpu/drm/msm/
H A Dmsm_iommu.c600 * It appears the hw drops writes to the PRR region in msm_iommu_pagetable_create()
602 * is in the PRR page. in msm_iommu_pagetable_create()
H A Dmsm_gem_vma.c34 /** @sgt: pages to map, or NULL for a PRR mapping */
1039 ret = UERR(EINVAL, dev, "PRR not supported\n"); in lookup_op()
/linux/arch/sh/mm/
H A Dcache-sh4.c385 printk("PVR=%08x CVR=%08x PRR=%08x\n", in sh4_cache_init()
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7792.dtsi952 prr: chipid@ff000044 { label
953 compatible = "renesas,prr";
H A Dr8a77470.dtsi1020 prr: chipid@ff000044 { label
1021 compatible = "renesas,prr";
H A Dr8a7794.dtsi1445 prr: chipid@ff000044 { label
1446 compatible = "renesas,prr";
H A Dr8a7793.dtsi1459 prr: chipid@ff000044 { label
1460 compatible = "renesas,prr";
H A Dr8a7745.dtsi1594 prr: chipid@ff000044 { label
1595 compatible = "renesas,prr";
H A Dr8a7744.dtsi1770 prr: chipid@ff000044 { label
1771 compatible = "renesas,prr";
H A Dr8a7743.dtsi1784 prr: chipid@ff000044 { label
1785 compatible = "renesas,prr";
H A Dr8a7742.dtsi1876 prr: chipid@ff000044 { label
1877 compatible = "renesas,prr";
H A Dr8a7791.dtsi1880 prr: chipid@ff000044 { label
1881 compatible = "renesas,prr";

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