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/linux/drivers/net/ethernet/ti/
H A Dam65-cpsw-qos.h53 #define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri)) argument
54 #define AM65_CPSW_P0_REG_PRI_EIR(pri) (0x160 + 4 * (pri)) argument
61 #define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri)) argument
62 #define AM65_CPSW_PN_REG_PRI_EIR(pri) (0x160 + 4 * (pri)) argument
145 #define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri)) argument
146 #define AM65_CPSW_PN_REG_PRI_EIR(pri) (0x160 + 4 * (pri)) argument
/linux/drivers/isdn/mISDN/
H A Dclock.c55 int pri = -128; in select_iclock() local
58 if (iclock->pri > pri) { in select_iclock()
59 pri = iclock->pri; in select_iclock()
87 *mISDN_register_clock(char *name, int pri, clockctl_func_t *ctl, void *priv) in mISDN_register_clock() argument
93 printk(KERN_DEBUG "%s: %s %d\n", __func__, name, pri); in mISDN_register_clock()
100 iclock->pri = pri; in mISDN_register_clock()
118 iclock->pri); in mISDN_unregister_clock()
H A Dl1oip_core.c14 Value 2 = PRI
16 Value 4 = PRI (multi channel frame, not supported yet)
34 PRI: 1-30, 31-126 (126, because dchannel ist not counted here)
36 It is possible to have more channels than 30 in PRI mode, this must
297 | (hc->pri ? 0x20 : 0x00) /* type */ in l1oip_socket_send()
474 if (((*buf) & 0x20) && !hc->pri) { in l1oip_socket_parse()
479 if (!((*buf) & 0x20) && hc->pri) { in l1oip_socket_parse()
1015 ch = rq->adr.channel; /* BRI: 1=B1 2=B2 PRI: 1..15,17.. */ in open_bchannel()
1049 if (hc->pri) { in l1oip_dctrl()
1057 if (!hc->pri) { in l1oip_dctrl()
[all …]
H A Dl1oip.h54 int pri; /* 1=pri, 0=bri */ member
/linux/drivers/net/wireless/ath/
H A Ddfs_pri_detector.h25 * struct pri_sequence - sequence of pulses matching one PRI
27 * @pri: pulse repetition interval (PRI) in usecs
37 u32 pri; member
47 * struct pri_detector - PRI detector element for a dedicated radar type
H A Ddfs_pri_detector.c236 /* ignore too small pri */ in pseq_handler_create_sequences()
240 /* stop on too large pri (sorted list) */ in pseq_handler_create_sequences()
243 /* build a new sequence with new potential pri */ in pseq_handler_create_sequences()
248 ps.pri = GET_PRI_TO_USE(pde->rs->pri_min, in pseq_handler_create_sequences()
250 ps.dur = ps.pri * (pde->rs->ppb - 1) in pseq_handler_create_sequences()
262 /* check if pulse match (multi)PRI */ in pseq_handler_create_sequences()
263 factor = pde_get_multiple(ps.last_ts - p2->ts, ps.pri, in pseq_handler_create_sequences()
320 factor = pde_get_multiple(delta_ts, ps->pri, in pseq_handler_add_to_existing_seqs()
/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal1.h174 /* Offset 0x10: IP-PRI Mapping Register 0
175 * Offset 0x11: IP-PRI Mapping Register 1
176 * Offset 0x12: IP-PRI Mapping Register 2
177 * Offset 0x13: IP-PRI Mapping Register 3
178 * Offset 0x14: IP-PRI Mapping Register 4
179 * Offset 0x15: IP-PRI Mapping Register 5
180 * Offset 0x16: IP-PRI Mapping Register 6
181 * Offset 0x17: IP-PRI Mapping Register 7
192 /* Offset 0x18: IEEE-PRI Register */
H A Dglobal1.c307 /* Offset 0x10: IP-PRI Mapping Register 0
308 * Offset 0x11: IP-PRI Mapping Register 1
309 * Offset 0x12: IP-PRI Mapping Register 2
310 * Offset 0x13: IP-PRI Mapping Register 3
311 * Offset 0x14: IP-PRI Mapping Register 4
312 * Offset 0x15: IP-PRI Mapping Register 5
313 * Offset 0x16: IP-PRI Mapping Register 6
314 * Offset 0x17: IP-PRI Mapping Register 7
357 /* Offset 0x18: IEEE-PRI Register */
/linux/include/linux/mtd/
H A Dcfi.h144 /* Extended Query Structure for both PRI and ALT */
147 uint8_t pri[3]; member
152 /* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */
155 uint8_t pri[3]; member
205 /* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */
208 uint8_t pri[3]; member
231 /* Vendor-Specific PRI for Atmel chips (command set 0x0002) */
234 uint8_t pri[3]; member
/linux/arch/x86/kernel/cpu/
H A Dhypervisor.c68 uint32_t pri, max_pri = 0; in detect_hypervisor_vendor() local
74 pri = (*p)->detect(); in detect_hypervisor_vendor()
75 if (pri > max_pri) { in detect_hypervisor_vendor()
76 max_pri = pri; in detect_hypervisor_vendor()
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dcb.c176 u32 pri = MAX_PFC_PRIORITIES; in bnx2x_dcbx_get_ap_priority() local
182 while ((MAX_PFC_PRIORITIES == pri) && (0 != index)) { in bnx2x_dcbx_get_ap_priority()
185 pri = index ; in bnx2x_dcbx_get_ap_priority()
189 if (pri < MAX_PFC_PRIORITIES) in bnx2x_dcbx_get_ap_priority()
190 ttp[llfc_traf_type] = max_t(u32, ttp[llfc_traf_type], pri); in bnx2x_dcbx_get_ap_priority()
584 ets_params.cos[i].params.sp_params.pri = in bnx2x_dcbx_update_ets_config()
684 u8 pri; in bnx2x_dcbx_dcbnl_app_up() local
687 for (pri = MAX_PFC_PRIORITIES - 1; pri > 0; pri--) in bnx2x_dcbx_dcbnl_app_up()
688 if (ent->pri_bitmap & (1 << pri)) in bnx2x_dcbx_dcbnl_app_up()
690 return pri; in bnx2x_dcbx_dcbnl_app_up()
[all …]
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_init.c862 u8 pri; in get_ctlr_pribits() local
868 pri = FIELD_GET(ICC_CTLR_EL1_PRI_BITS_MASK, val) + 1; in get_ctlr_pribits()
869 TEST_ASSERT(pri >= 5 && pri <= 7, "Bad pribits %d", pri); in get_ctlr_pribits()
871 return pri; in get_ctlr_pribits()
901 u8 pri; in get_vtr_pribits() local
907 pri = FIELD_GET(ICH_VTR_EL2_PRIbits, val) + 1; in get_vtr_pribits()
908 TEST_ASSERT(pri >= 5 && pri < in get_vtr_pribits()
[all...]
/linux/arch/mips/include/asm/
H A Dcop2.h51 #define cu2_notifier(fn, pri) \ argument
55 .priority = pri \
H A Dtraps.h32 #define nmi_notifier(fn, pri) \ argument
36 .priority = pri \
/linux/tools/testing/selftests/powerpc/nx-gzip/
H A Dgzip_vas.c51 static int open_device_nodes(char *devname, int pri, struct nx_handle *handle) in open_device_nodes() argument
65 txattr.vas_id = pri; in open_device_nodes()
88 void *nx_function_begin(int function, int pri) in nx_function_begin() argument
109 rc = open_device_nodes(devname, pri, nxhandle); in nx_function_begin()
/linux/drivers/net/ethernet/broadcom/bnxt/
H A Dbnxt_dcb.c254 u8 i, pri, lltc_count = 0; in bnxt_hwrm_queue_pfc_cfg() local
262 for (pri = 0; pri < IEEE_8021QAZ_MAX_TCS; pri++) { in bnxt_hwrm_queue_pfc_cfg()
263 if ((pfc->pfc_en & (1 << pri)) && in bnxt_hwrm_queue_pfc_cfg()
264 (my_ets->prio_tc[pri] == i)) { in bnxt_hwrm_queue_pfc_cfg()
265 pri_mask |= 1 << pri; in bnxt_hwrm_queue_pfc_cfg()
466 dscp2pri->pri = app->priority; in bnxt_hwrm_queue_dscp2pri_cfg()
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_dfs.c436 int i, j, end, pri, factor, cur_pri; in mt76x02_dfs_create_sequence() local
470 pri = event->ts - cur_event->ts; in mt76x02_dfs_create_sequence()
472 pri < sw_params->min_pri) in mt76x02_dfs_create_sequence()
475 if (pri > sw_params->max_pri) in mt76x02_dfs_create_sequence()
478 seq.pri = event->ts - cur_event->ts; in mt76x02_dfs_create_sequence()
488 factor = mt76x02_dfs_get_multiple(cur_pri, seq.pri, in mt76x02_dfs_create_sequence()
520 int factor, pri; in mt76x02_dfs_add_event_to_sequence() local
533 pri = event->ts - seq->last_ts; in mt76x02_dfs_add_event_to_sequence()
534 factor = mt76x02_dfs_get_multiple(pri, seq->pri, in mt76x02_dfs_add_event_to_sequence()
/linux/drivers/crypto/cavium/cpt/
H A Dcptpf_mbox.c50 static void cpt_cfg_vq_priority(struct cpt_device *cpt, int vf, u32 pri) in cpt_cfg_vq_priority() argument
55 pf_qx_ctl.s.pri = pri; in cpt_cfg_vq_priority()
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu-v3.yaml16 and event queues and adding support for the ATS and PRI components of
46 - priq # PRI Queue not empty
/linux/Documentation/arch/x86/
H A Dsva.rst18 (PRI) allow devices to function much the same way as the CPU handling
23 required to support the PCIe features ATS and PRI. ATS allows devices
27 use the PRI in order to request the virtual address to be paged into the
83 present, the device would request the page to be paged in via the PCIe PRI
264 Interface (PRI). Once the OS has successfully completed the mapping, it
/linux/drivers/iommu/intel/
H A Dsvm.c133 * support PCI/PRI. The IOMMU side has no means to check the in intel_iommu_sva_supported()
135 * default that if the device driver enables SVA on a non-PRI in intel_iommu_sva_supported()
141 /* Devices supporting PRI should have it enabled. */ in intel_iommu_sva_supported()
/linux/include/linux/
H A Dmemory.h146 static inline int hotplug_memory_notifier(notifier_fn_t fn, int pri) in hotplug_memory_notifier() argument
181 #define hotplug_memory_notifier(fn, pri) ({ \ argument
183 { .notifier_call = fn, .priority = pri };\
/linux/fs/isofs/
H A Dinode.c578 struct iso_primary_descriptor *pri = NULL; in isofs_fill_super() local
642 if (!pri) { in isofs_fill_super()
643 pri = (struct iso_primary_descriptor *)vdp; in isofs_fill_super()
693 if (!pri) in isofs_fill_super()
706 if (joliet_level && (!pri || !opt->rock)) { in isofs_fill_super()
710 pri = (struct iso_primary_descriptor *) sec; in isofs_fill_super()
719 if (!pri) in isofs_fill_super()
721 rootp = (struct iso_directory_record *) pri->root_directory_record; in isofs_fill_super()
722 sbi->s_nzones = isonum_733(pri->volume_space_size); in isofs_fill_super()
723 sbi->s_log_zone_size = isonum_723(pri->logical_block_size); in isofs_fill_super()
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_tm.c228 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id) in hclge_fill_pri_array() argument
246 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4); in hclge_fill_pri_array()
254 u8 *pri = (u8 *)desc.data; in hclge_up_to_tc_map() local
261 ret = hclge_fill_pri_array(hdev, pri, pri_id); in hclge_up_to_tc_map()
326 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev, u16 qs_id, u8 pri, in hclge_tm_qs_to_pri_map_cfg() argument
337 map->priority = pri; in hclge_tm_qs_to_pri_map_cfg()
895 /* Pg to pri */ in hclge_tm_pg_shaper_cfg()
979 /* Cfg qs -> pri mapping, one by one mapping */ in hclge_tm_pri_q_qs_cfg_tc_base()
984 u8 pri = i < kinfo->tc_info.num_tc ? i : 0; in hclge_tm_pri_q_qs_cfg_tc_base() local
989 pri, link_vld); in hclge_tm_pri_q_qs_cfg_tc_base()
[all …]
/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf_mbox.c126 static void otx_cpt_cfg_vq_priority(struct otx_cpt_device *cpt, int vf, u32 pri) in otx_cpt_cfg_vq_priority() argument
131 pf_qx_ctl.s.pri = pri; in otx_cpt_cfg_vq_priority()

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