Searched full:ppis (Results 1 – 17 of 17) sorted by relevance
24 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
108 * as the per-vCPU arrays of private IRQs (SGIs, PPIs). in kvm_vgic_create()281 * configure all PPIs as level-triggered. in vgic_allocate_private_irqs_locked()297 /* PPIs */ in vgic_allocate_private_irqs_locked()
108 /* SGIs and PPIs */ in vgic_get_vcpu_irq()499 * @vcpu: The CPU for PPIs or NULL for global interrupts671 * @vcpu: Pointer to the VCPU (used for PPIs)
746 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer in vgic_mmio_write_config()747 * code relies on PPIs being level triggered, so we also in vgic_mmio_write_config()
229 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs in vgic_set_common_attr()
601 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
87 * on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
98 /* can inject PPIs, PPIs, and/or SPIs. */463 /* Timer PPIs cannot be injected from userspace */ in test_preemption()
135 /* Misconfigured PPIs are usually not fatal */ in hip04_irq_set_type()
729 /* Misconfigured PPIs are usually not fatal */ in gic_set_type()1127 pr_info("GICv3 features: %d PPIs%s%s\n", in gic_update_rdist_properties()1292 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
308 /* Misconfigured PPIs are usually not fatal */ in gic_set_type()
336 /* Set a default priority for all the SGIs and PPIs */ in gicv3_cpu_init()
352 PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
950 u8 ppi_flags; /* valid/present bits for the above PPIs */
396 /* Copy the PPIs into nvchan->recv_buf */ in rndis_get_ppi()
1304 /* Request our PPIs (note that the IRQ is still disabled) */ in arm_spe_pmu_dev_init()