Searched full:ppis (Results 1 – 21 of 21) sorted by relevance
124 /* Read out the PPIs that user space is allowed to drive. */ in test_vgic_v5_ppis()168 TEST_ASSERT(ret == 0, "Failed to test GICv5 PPIs"); in test_vgic_v5_ppis()204 pr_info("Test VGICv5 PPIs\n"); in run_tests()
98 /* can inject PPIs, PPIs, and/or SPIs. */463 /* Timer PPIs cannot be injected from userspace */ in test_preemption()
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
107 * as the per-vCPU arrays of private IRQs (SGIs, PPIs). in kvm_vgic_create()290 /* PPIs */ in vgic_allocate_private_irq()354 * configure all PPIs as level-triggered. in vgic_allocate_private_irqs_locked()
124 /* SGIs and PPIs */ in vgic_get_vcpu_irq()518 * @vcpu: The CPU for PPIs or NULL for global interrupts712 * @vcpu: Pointer to the VCPU (used for PPIs)
601 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
87 * on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
135 /* Misconfigured PPIs are usually not fatal */ in hip04_irq_set_type()
507 * GICv5's PPIs do not have a configurable trigger or handling in gicv5_ppi_irq_set_type()625 * Handling mode is hardcoded for PPIs, set the type using in gicv5_irq_domain_translate()
308 /* Misconfigured PPIs are usually not fatal */ in gic_set_type()
28 * Architected PPIs
336 /* Set a default priority for all the SGIs and PPIs */ in gicv3_cpu_init()
352 PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
950 u8 ppi_flags; /* valid/present bits for the above PPIs */
396 /* Copy the PPIs into nvchan->recv_buf */ in rndis_get_ppi()
1304 /* Request our PPIs (note that the IRQ is still disabled) */ in arm_spe_pmu_dev_init()
1716 * We present a different subset of PPIs the guest from what in __compute_ich_hfgwtr()
734 * If we're only handling architected PPIs and the guest writes to the in access_gicv5_ppi_enabler()735 * enable for the non-architected PPIs, we just return as there's in access_gicv5_ppi_enabler()752 * PPIs as we don't expose many to the guest. in access_gicv5_ppi_enabler()
1511 * Only allow PPIs that are explicitly exposed to in kvm_vm_ioctl_irq_line()
358 /* Timer PPIs made immutable */
899 use PPIs designated for specific cpus. The irq field is interpreted