Searched full:ppis (Results 1 – 13 of 13) sorted by relevance
122 /* Read out the PPIs that user space is allowed to drive. */ in test_vgic_v5_ppis() 168 TEST_ASSERT(ret == 0, "Failed to test GICv5 PPIs"); in test_vgic_v5_ppis() 204 pr_info("Test VGICv5 PPIs\n"); in run_tests()
98 /* can inject PPIs, PPIs, and/or SPIs. */463 /* Timer PPIs cannot be injected from userspace */ in test_preemption()
87 * on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
135 /* Misconfigured PPIs are usually not fatal */ in hip04_irq_set_type()
491 * GICv5's PPIs do not have a configurable trigger or handling in gicv5_ppi_irq_set_type()611 * Handling mode is hardcoded for PPIs, set the type using in gicv5_irq_domain_translate()
217 /* Skip SGIs and PPIs*/ in xgene_gpio_sb_domain_alloc()
336 /* Set a default priority for all the SGIs and PPIs */ in gicv3_cpu_init()
352 PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
71 /* Maximum number of PPIs per coalesced CQE */
601 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
952 u8 ppi_flags; /* valid/present bits for the above PPIs */
396 /* Copy the PPIs into nvchan->recv_buf */ in rndis_get_ppi()
1304 /* Request our PPIs (note that the IRQ is still disabled) */ in arm_spe_pmu_dev_init()