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/linux/Documentation/devicetree/bindings/powerpc/opal/
H A Dpower-mgt.txt49 0x00010000 /* This is a nap state (POWER7,POWER8) */
50 0x00020000 /* This is a fast-sleep state (POWER8)*/
51 0x00040000 /* This is a winkle state (POWER8) */
54 /* timebase (POWER8) */
56 /* (POWER8)*/
68 ibm,cpu-idle-state-names. On POWER8 this is an optional
76 This property is required on POWER9 and absent on POWER8.
82 required on POWER9 and absent on POWER8.
111 is an optional property on POWER8 and is absent on
118 property on POWER8 and is absent on POWER9.
/linux/arch/powerpc/kernel/
H A Dcpu_specs_book3s_64.h229 { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
232 .cpu_name = "POWER8 (architected)",
242 .platform = "power8",
257 .platform = "power8",
350 .platform = "power8",
367 .platform = "power8",
369 { /* Power8 */
372 .cpu_name = "POWER8 (raw)",
384 .platform = "power8",
/linux/arch/powerpc/perf/
H A Dpower8-pmu.c3 * Performance counter support for POWER8 processors.
9 #define pr_fmt(fmt) "power8-pmu: " fmt
14 * Some power8 event codes.
19 #include "power8-events-list.h"
24 /* MMCRA IFM bits - POWER8 */
31 * Raw event encoding for PowerISA v2.07 (Power8):
370 .name = "POWER8",
H A Dpower8-events-list.h3 * Performance counter support for POWER8 processors.
9 * Power8 event codes.
H A Dhv-gpci.h8 * 8 => power8 (1.07)
H A Dbhrb.S16 * is 1024. We have limited number of table entries here as POWER8 implements
/linux/Documentation/arch/powerpc/
H A Disa-versions.rst14 Power8 Power ISA v2.07
48 Power8 Yes
68 Power8 Yes
88 Power8 Yes
H A Ddawr-power9.rst43 migration from POWER8 to POWER9, at the cost of silently losing the
60 If a guest is started on a POWER8 host, GDB will accept the watchpoint
66 migrated back to the POWER8 host, it will start working again.
H A Dtransactional_memory.rst15 Hardware Transactional Memory is supported on POWER8 processors, and is a
245 Guest migration from POWER8 to POWER9 will work with POWER9N DD2.2 and
247 emulation, migration from POWER8 to POWER9 is not supported there.
H A Ddscr.rst60 (1) Problem state SPR: 0x03 (Un-privileged, POWER8 only)
/linux/drivers/hwmon/occ/
H A DKconfig7 tristate "POWER8 OCC through I2C"
12 On-Chip Controller (OCC) on a POWER8 processor. However, this driver
/linux/tools/perf/pmu-events/
H A DREADME46 is derived from JSON file name, 'power8.json').
95 where 'pm_1plus_ppc_cmpl' is a Power8 PMU event.
/linux/tools/testing/kunit/qemu_configs/
H A Dpowerpc.py13 extra_qemu_params=['-M', 'pseries', '-cpu', 'power8'])
/linux/arch/arm/mach-aspeed/
H A DKconfig22 fourth generation BMCs, such as those used by OpenPower Power8
/linux/tools/testing/selftests/powerpc/math/
H A Dfpu_denormal.c5 * This test attempts to cause a FP denormal exception on POWER8 CPUs. Unfortunately
/linux/tools/testing/selftests/powerpc/pmu/
H A Dl3_bank_test.c23 // The L3 bank logic is only used on Power8 or later in l3_bank_test()
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-opal.txt30 compatible = "ibm,power8-i2c-port", "ibm,opal-i2c";
/linux/arch/powerpc/xmon/
H A Dppc.h191 /* Opcode is only supported by Power8 architecture. */
195 /* Currently, this is the same as the POWER8 mask. If another cpu comes out
196 that isn't a superset of POWER8, we can define this to its own mask. */
/linux/Documentation/devicetree/bindings/tpm/
H A Dibm,vtpm.yaml13 Virtual TPM is used on IBM POWER7+ and POWER8 systems running POWERVM.
/linux/arch/powerpc/include/asm/
H A Dcache.h27 #define IFETCH_ALIGN_SHIFT 4 /* POWER8,9 */
H A Dcpuidle.h13 * Core state used in powernv idle for POWER8.
/linux/arch/powerpc/platforms/powernv/
H A Dopal-lpc.c389 * Look for a Power8 LPC bus tagged as "primary", in opal_lpc_init()
393 for_each_compatible_node(np, NULL, "ibm,power8-lpc") { in opal_lpc_init()
/linux/lib/raid6/
H A Dvpermxor.uc20 * This instruction was introduced in POWER8 - ISA v2.07.
/linux/arch/powerpc/platforms/pseries/
H A Dpmem.c149 * Only supported on POWER8 and above. in pseries_pmem_init()
/linux/Documentation/hwmon/
H A Docc.rst6 * POWER8

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