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/linux/arch/x86/events/amd/
H A Duncore.c75 struct amd_uncore_pmu *pmus; member
105 * Some uncore PMUs do not have RDPMC assignments. In such cases, in amd_uncore_read()
425 pmu = &uncore->pmus[i]; in amd_uncore_ctx_free()
455 pmu = &uncore->pmus[i]; in amd_uncore_ctx_init()
519 pmu = &uncore->pmus[i]; in amd_uncore_ctx_move()
672 uncore->pmus = kzalloc(sizeof(*uncore->pmus), GFP_KERNEL); in amd_uncore_df_ctx_init()
673 if (!uncore->pmus) in amd_uncore_df_ctx_init()
678 * as Data Fabric counters. The PMUs are exported based on family as in amd_uncore_df_ctx_init()
681 pmu = &uncore->pmus[0]; in amd_uncore_df_ctx_init()
806 uncore->pmus = kzalloc(sizeof(*uncore->pmus), GFP_KERNEL); in amd_uncore_l3_ctx_init()
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/linux/tools/perf/Documentation/
H A Dperf-list.txt182 ARBITRARY PMUS
186 to PMUs. Using this typically requires looking up the specific event
189 The available PMUs and their raw parameters can be listed with
202 PER SOCKET PMUS
205 Some PMUs are not associated with a core, but with a whole CPU socket.
206 Events on these PMUs generally cannot be sampled, but only counted globally
216 bandwidth would require specifying all imc PMUs (see perf list output),
236 Other PMUs and global measurements are normally root only.
249 Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
307 Events from multiple different PMUs canno
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H A Dperf-stat.txt64 of the same type of PMU in large systems (e.g. memory controller PMUs).
65 Multiple PMU instances are typical for uncore PMUs, so the prefix
437 Do not aggregate/merge counts across monitored CPUs or PMUs.
451 example, multiple memory controller PMUs may exist typically with a
460 Merge core event counts from all core PMUs. In hybrid or big.LITTLE
H A Dperf-amd-ibs.txt26 Both, IBS Op and IBS Fetch, are exposed as PMUs by Linux and can be exploited
36 IBS PMUs do not have user/kernel filtering capability and thus it requires
H A Dintel-hybrid.txt10 Kernel exports two new cpu pmus via sysfs:
203 warning and disable grouping, because the pmus in group are
/linux/tools/perf/pmu-events/
H A Djevents.py507 pmus = set()
519 pmus.add((event.pmu, pmu_name))
530 for (pmu, tbl_pmu) in sorted(pmus):
565 pmus = set()
575 pmus.add((metric.pmu, pmu_name))
585 for (pmu, tbl_pmu) in sorted(pmus):
679 const struct pmu_table_entry *pmus;
685 const struct pmu_table_entry *pmus;
716 \t\t.pmus = pmu_events__test_soc_cpu,
720 \t\t.pmus
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H A Dempty-pmu-events.c183 const struct pmu_table_entry *pmus;
189 const struct pmu_table_entry *pmus;
217 .pmus = pmu_events__test_soc_cpu,
221 .pmus = pmu_metrics__test_soc_cpu,
242 .pmus = pmu_events__test_soc_sys,
375 const struct pmu_table_entry *table_pmu = &table->pmus[i]; in perf_pmu__find_metrics_table()
396 const struct pmu_table_entry *table_pmu = &table->pmus[i]; in find_core_events_table()
416 const struct pmu_table_entry *table_pmu = &table->pmus[i]; in pmu_for_each_core_event()
451 int ret = pmu_metrics_table__for_each_metric_pmu(table, &table->pmus[i], in pmu_for_each_sys_event()
482 * PMUs othe
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/linux/tools/perf/arch/arm/util/
H A Dauxtrace.c17 #include "../../../util/pmus.h"
102 static struct perf_pmu *find_pmu_for_event(struct perf_pmu **pmus, in find_pmu_for_event() argument
107 if (!pmus) in find_pmu_for_event()
111 if (evsel->core.attr.type == pmus[i]->type) in find_pmu_for_event()
112 return pmus[i]; in find_pmu_for_event()
/linux/Documentation/admin-guide/perf/
H A Dqcom_l3_pmu.rst5 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
12 options in sysfs, see /sys/bus/event_source/devices/l3cache*. Given that these are uncore PMUs
25 Given that these are uncore PMUs the driver does not support sampling, therefore
H A Dthunderx2-pmu.rst6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
23 (CCPI2) events simultaneously. The PMUs provide a description of their
H A Dxgene-pmu.rst5 X-Gene SoC PMU consists of various independent system device PMUs such as
8 same model as the PMU for ARM cores. The PMUs share the same top level
H A Dalibaba_pmu.rst15 implements separate PMUs for each sub-channel to monitor various performance
50 to and from the SDRAM. The driveway PMUs have hardware logic to gather
H A Dhisi-pmu.rst5 The HiSilicon SoC chip includes various independent system device PMUs
6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
H A Darm_dsu_pmu.rst11 cores connected to the same DSU. Like most of the other uncore PMUs, DSU
/linux/tools/perf/util/
H A Dpmus.c16 #include "pmus.h"
23 * directory contains "cpus" file. All PMUs belonging to core_pmus
29 * other_pmus: All other PMUs which are not part of core_pmus list. It doesn't
32 * ibs_op// PMUs is present in each hw SMT thread, however they
33 * are captured under other_pmus. PMUs belonging to other_pmus
155 * an alias, so read the PMUs from sysfs and try to find again. in perf_pmus__find()
197 /* Add all pmus in sysfs to pmu list: */
229 pr_err("Failure to set up any core PMUs\n"); in pmu_read_sysfs()
353 /* Ignore "cpu_" prefix on Intel hybrid PMUs. */ in perf_pmus__pmu_for_pmu_filter()
417 /* Don't remove duplicates for different PMUs */ in pmu_alias_is_duplicate()
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H A Dmem-events.c19 #include "pmus.h"
59 * mem_events supported PMUs. in perf_mem_events_find_pmu()
63 * supported PMUs is Intel hybrid. The exact same mem_events in perf_mem_events_find_pmu()
64 * is shared among the PMUs. Only configure the first PMU in perf_mem_events_find_pmu()
71 * perf_pmu__mem_events_num_mem_pmus - Get the number of mem PMUs since the given pmu
/linux/arch/x86/kvm/vmx/
H A Dpmu_intel.c24 * Perf's "BASE" is wildly misleading, architectural PMUs use bits 31:16 of ECX
26 * further confuse things, non-architectural PMUs use bit 31 as a flag for
69 * non-architecturals PMUs (PMUs with version '0'). For architectural in intel_rdpmc_ecx_to_pmc()
70 * PMUs, bits 31:16 specify the PMC type and bits 15:0 specify the PMC in intel_rdpmc_ecx_to_pmc()
71 * index. For non-architectural PMUs, bit 31 is a "fast" flag, and in intel_rdpmc_ecx_to_pmc()
75 * as KVM doesn't support such PMUs. in intel_rdpmc_ecx_to_pmc()
81 * General Purpose (GP) PMCs are supported on all PMUs, and fixed PMCs in intel_rdpmc_ecx_to_pmc()
82 * are supported on all architectural PMUs, i.e. on all virtual PMUs in intel_rdpmc_ecx_to_pmc()
/linux/tools/lib/perf/include/internal/
H A Devsel.h47 * The cpu map read from the PMU. For core PMUs this is the list of all
48 * CPUs the event can be opened upon. For other PMUs this is the default
/linux/arch/powerpc/include/asm/
H A Dimc-pmu.h110 * registers new IMC pmus. This structure will hold the
159 * Domains for IMC PMUs
/linux/arch/x86/kvm/
H A Dpmu.h189 * Hybrid PMUs don't play nice with virtualization without careful in kvm_init_pmu_capability()
191 * vPMU features do not account for hybrid PMUs. Disable vPMU support in kvm_init_pmu_capability()
192 * for hybrid PMUs until KVM gains a way to let userspace opt-in. in kvm_init_pmu_capability()
/linux/tools/perf/tests/
H A Devent_groups.c9 #include "pmus.h"
19 /* Uncore pmus that support more than 3 counters */
/linux/drivers/perf/
H A Dqcom_l2_pmu.c107 * the hardware PMUs.
123 * This structure represents one of the hardware PMUs.
424 * physical PMUs (per cluster), because we do not support per-task mode in l2_cache_pmu_enable()
471 /* Don't allow groups with mixed PMUs, except for s/w events */ in l2_cache_event_init()
939 dev_err(&pdev->dev, "No hardware L2 cache PMUs found\n"); in l2_cache_pmu_probe()
956 dev_info(&pdev->dev, "Registered L2 cache PMU using %d HW PMUs\n", in l2_cache_pmu_probe()
/linux/include/linux/regulator/
H A Dact8865.h3 * act8865.h -- Voltage regulation for active-semi act88xx PMUs
/linux/tools/perf/arch/x86/util/
H A Dtopdown.c5 #include "util/pmus.h"
/linux/tools/perf/arch/arm64/util/
H A Dpmu.c7 #include "../../../util/pmus.h"

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