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/linux/drivers/clk/baikal-t1/
H A Dclk-ccu-pll.c57 * Alas we have to mark all PLLs as critical. CPU and DDR PLLs are sources of
59 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
61 * unusable. Moreover disabling SATA and Ethernet PLLs causes automatic reset
63 * all the devices consuming those PLLs, they will be marked as critical too.
81 struct ccu_pll *plls[CCU_PLL_NUM]; member
93 return data->plls[idx]; in ccu_pll_find_desc()
156 /* Defer non-basic PLLs allocation for the probe stage */ in ccu_pll_clk_register()
158 if (!data->plls[idx]) in ccu_pll_clk_register()
159 data->plls[idx] = ERR_PTR(-EPROBE_DEFER); in ccu_pll_clk_register()
173 data->plls[idx] = ccu_pll_hw_register(&init); in ccu_pll_clk_register()
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H A DKconfig11 in them are fed with clocks generated by a hierarchy of PLLs,
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
23 System Controller. These are five PLLs placed at the root of the
36 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
/linux/Documentation/devicetree/bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
22 in general can provide any frequency supported by the CCU PLLs).
23 2) PLLs clocks generators (PLLs) - described in this binding file.
31 | +-|PLLs|------|- DDR controller
47 output is primarily connected to a set of CCU PLLs. There are five PLLs
51 peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
53 the PLL configuration procedure. The PLLs work as depicted on the next
77 The PLLs CLKOUT is then either directly connected with the corresponding
H A Damlogic,axg-audio-clkc.yaml38 - description: input plls to generate clock signals N0
39 - description: input plls to generate clock signals N1
40 - description: input plls to generate clock signals N2
41 - description: input plls to generate clock signals N3
42 - description: input plls to generate clock signals N4
43 - description: input plls to generate clock signals N5
44 - description: input plls to generate clock signals N6
45 - description: input plls to generate clock signals N7
H A Dbaikal,bt1-ccu-div.yaml19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
24 in general can provide any frequency supported by the CCU PLLs).
25 2) PLLs clocks generators (PLLs).
34 | +-|PLLs|------|- DDR controller
50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
66 where CLKIN is the reference clock coming either from CCU PLLs or from an
H A Dstarfive,jh7110-pll.yaml10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
12 registers in the sys syscon. So the PLLs node should be a child of
H A Dmediatek,mt8188-sys-clock.yaml14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
H A Dmediatek,mt8186-sys-clock.yaml14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
H A Dmediatek,mt8195-sys-clock.yaml14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
H A Dst,nomadik.txt7 PLLs and clock gates.
23 PLL nodes: these nodes represent the two PLLs on the system,
H A Dmediatek,mt8196-sys-clock.yaml15 PLLs -->
22 provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
H A Dmediatek,mt8195-clock.yaml14 PLLs -->
21 The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
/linux/drivers/clk/bcm/
H A Dclk-iproc.h36 * Some PLLs require the PLL SW override bit to be set before changes can be
42 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
48 * Some PLLs have separate registers for Status and Control. Identify this to
54 * Some PLLs have an additional divide by 2 in master clock calculation;
61 * Some PLLs provide a look up table for the leaf clock frequencies and
69 * Some PLLs have an active low reset
181 * Main clock control parameters for clocks derived from the PLLs
/linux/drivers/clk/thead/
H A DKconfig12 both CPU PLLs, both DPU PLLs as well as the GMAC, VIDEO,
13 and TEE PLLs.
/linux/drivers/clk/
H A Dclk-eyeq.c6 * - Read-only PLLs, all derived from the same main crystal clock.
7 * - It also exposes divider clocks, those are children to PLLs.
8 * - Fixed factor clocks, children to PLLs.
11 * shared region called OLB. Some PLLs and fixed-factors are initialised early
102 const struct eqc_pll *plls; member
240 pll = &data->plls[i]; in eqc_probe_init_plls()
409 /* Early PLLs are marked as errors: the early provider will get queried. */ in eqc_probe()
547 .plls = eqc_eyeq5_plls,
571 .plls = eqc_eyeq6l_plls,
586 .plls = eqc_eyeq6h_east_plls,
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H A Dclk-k210.c281 * PLLs.
300 * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
325 * @plls: SoC PLLs descriptors
332 struct k210_pll plls[K210_PLL_NUM]; member
549 struct k210_pll *pll = &ksc->plls[pllid]; in k210_register_pll()
553 { .hw = &ksc->plls[K210_PLL0].hw }, in k210_register_pll()
554 { .hw = &ksc->plls[K210_PLL1].hw }, in k210_register_pll()
574 k210_init_pll(ksc->regs, i, &ksc->plls[i]); in k210_register_plls()
653 { .hw = &ksc->plls[K210_PLL0].hw }, in k210_register_aclk()
828 { .hw = &ksc->plls[K210_PLL0].hw } in k210_register_mux_clk()
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dpll.c32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
50 dss->plls[i] = NULL; in dss_pll_unregister()
61 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_find()
62 if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0) in dss_pll_find()
63 return dss->plls[i]; in dss_pll_find()
/linux/drivers/clk/mediatek/
H A Dclk-pllfh.c201 const struct mtk_pll_data *plls, int num_plls, in mtk_clk_register_pllfhs() argument
216 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_pllfhs()
242 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_pllfhs()
263 void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls, in mtk_clk_unregister_pllfhs() argument
274 const struct mtk_pll_data *pll = &plls[i - 1]; in mtk_clk_unregister_pllfhs()
H A Dclk-pll.c415 const struct mtk_pll_data *plls, int num_plls, in mtk_clk_register_plls() argument
429 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_plls()
452 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_plls()
472 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, in mtk_clk_unregister_plls() argument
482 const struct mtk_pll_data *pll = &plls[i - 1]; in mtk_clk_unregister_plls()
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-zynqmp-fpga18 BIT(2) 0: MMCMs/PLLs are not locked
19 1: MMCMs/PLLs are locked
/linux/drivers/clk/spacemit/
H A Dccu_common.c143 * The lock status of PLLs locate in MPMU region, while PLLs themselves in spacemit_ccu_probe()
/linux/arch/arm/mach-tegra/
H A Dsleep-tegra20.S277 * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
282 * start by switching to CLKM to safely disable PLLs, then switch to
292 /* 2uS delay delay between changing SCLK and disabling PLLs */
/linux/drivers/clk/sunxi-ng/
H A Dccu_sdm.c80 * some PLLs support this. On later SoCs, all PLLs support this.
/linux/drivers/clk/qcom/
H A Dclk-cpu-8996.c8 * clocked via 2 PLLs, a primary and alternate. There are also
112 /* PLLs */
446 /* Ensure write goes through before PLLs are reconfigured */ in qcom_cpu_clk_msm8996_register_clks()
496 /* Enable alt PLLs */ in qcom_cpu_clk_msm8996_register_clks()
/linux/include/dt-bindings/clock/
H A Dingenic,jz4740-cgu.h7 * - PLLs

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