| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | amlogic,axg-audio-clkc.yaml | 38 - description: input plls to generate clock signals N0
39 - description: input plls to generate clock signals N1
40 - description: input plls to generate clock signals N2
41 - description: input plls to generate clock signals N3
42 - description: input plls to generate clock signals N4
43 - description: input plls to generate clock signals N5
44 - description: input plls to generate clock signals N6
45 - description: input plls to generate clock signals N7
|
| H A D | starfive,jh7110-pll.yaml | 10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
12 registers in the sys syscon. So the PLLs node should be a child of
|
| H A D | mediatek,mt8188-sys-clock.yaml | 14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
|
| H A D | mediatek,mt8186-sys-clock.yaml | 14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
|
| H A D | mediatek,mt8195-sys-clock.yaml | 14 PLLs -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
|
| H A D | st,nomadik.txt | 7 PLLs and clock gates.
23 PLL nodes: these nodes represent the two PLLs on the system,
|
| H A D | mediatek,mt8196-sys-clock.yaml | 15 PLLs -->
22 provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
|
| H A D | mediatek,mt8195-clock.yaml | 14 PLLs -->
21 The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
|
| H A D | toshiba,tmpv770x-pipllct.yaml | 13 Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X.
|
| /linux/drivers/clk/bcm/ |
| H A D | clk-iproc.h | 36 * Some PLLs require the PLL SW override bit to be set before changes can be
42 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
48 * Some PLLs have separate registers for Status and Control. Identify this to
54 * Some PLLs have an additional divide by 2 in master clock calculation;
61 * Some PLLs provide a look up table for the leaf clock frequencies and
69 * Some PLLs have an active low reset
181 * Main clock control parameters for clocks derived from the PLLs
|
| /linux/drivers/clk/thead/ |
| H A D | Kconfig | 12 both CPU PLLs, both DPU PLLs as well as the GMAC, VIDEO,
13 and TEE PLLs.
|
| /linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | pll.c | 32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
50 dss->plls[i] = NULL; in dss_pll_unregister()
61 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_find()
62 if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0) in dss_pll_find()
63 return dss->plls[i]; in dss_pll_find()
|
| /linux/drivers/clk/mediatek/ |
| H A D | clk-pllfh.c | 201 const struct mtk_pll_data *plls, int num_plls, in mtk_clk_register_pllfhs() argument
216 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_pllfhs()
242 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_pllfhs()
263 void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls, in mtk_clk_unregister_pllfhs() argument
274 const struct mtk_pll_data *pll = &plls[i - 1]; in mtk_clk_unregister_pllfhs()
|
| H A D | clk-pll.c | 415 const struct mtk_pll_data *plls, int num_plls, in mtk_clk_register_plls() argument
429 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_plls()
452 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_plls()
472 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, in mtk_clk_unregister_plls() argument
482 const struct mtk_pll_data *pll = &plls[i - 1]; in mtk_clk_unregister_plls()
|
| /linux/drivers/clk/ |
| H A D | clk-k210.c | 281 * PLLs.
300 * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
325 * @plls: SoC PLLs descriptors
332 struct k210_pll plls[K210_PLL_NUM]; member
549 struct k210_pll *pll = &ksc->plls[pllid]; in k210_register_pll()
553 { .hw = &ksc->plls[K210_PLL0].hw }, in k210_register_pll()
554 { .hw = &ksc->plls[K210_PLL1].hw }, in k210_register_pll()
574 k210_init_pll(ksc->regs, i, &ksc->plls[i]); in k210_register_plls()
653 { .hw = &ksc->plls[K210_PLL0].hw }, in k210_register_aclk()
828 { .hw = &ksc->plls[K210_PLL0].hw } in k210_register_mux_clk()
[all …]
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-zynqmp-fpga | 18 BIT(2) 0: MMCMs/PLLs are not locked
19 1: MMCMs/PLLs are locked
|
| /linux/drivers/clk/spacemit/ |
| H A D | ccu_common.c | 143 * The lock status of PLLs locate in MPMU region, while PLLs themselves in spacemit_ccu_probe()
|
| /linux/arch/arm/mach-tegra/ |
| H A D | sleep-tegra20.S | 277 * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
282 * start by switching to CLKM to safely disable PLLs, then switch to
292 /* 2uS delay delay between changing SCLK and disabling PLLs */
|
| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_sdm.c | 80 * some PLLs support this. On later SoCs, all PLLs support this.
|
| /linux/drivers/clk/qcom/ |
| H A D | clk-cpu-8996.c | 8 * clocked via 2 PLLs, a primary and alternate. There are also
112 /* PLLs */
446 /* Ensure write goes through before PLLs are reconfigured */ in qcom_cpu_clk_msm8996_register_clks()
496 /* Enable alt PLLs */ in qcom_cpu_clk_msm8996_register_clks()
|
| /linux/include/dt-bindings/clock/ |
| H A D | ingenic,jz4740-cgu.h | 7 * - PLLs
|
| H A D | marvell,pxa910.h | 5 /* fixed clocks and plls */
|
| H A D | ingenic,x1000-cgu.h | 7 * - PLLs
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | dra62x-clocks.dtsi | 5 /* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
|
| /linux/drivers/clk/keystone/ |
| H A D | Kconfig | 7 a power sleep control module that gate the clock to the IPs and PLLs.
|