| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | allwinner,sun9i-a80-pll4-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
20 const: allwinner,sun9i-a80-pll4-clk
44 compatible = "allwinner,sun9i-a80-pll4-clk";
47 clock-output-names = "pll4";
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| H A D | qcom,gcc-ipq8064.yaml | 34 - description: PLL4 from LCC
41 - const: pll4
66 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
67 clock-names = "pxo", "cxo", "pll4";
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| H A D | allwinner,sun9i-a80-apb0-clk.yaml | 50 clocks = <&osc24M>, <&pll4>;
59 clocks = <&osc24M>, <&pll4>;
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| H A D | allwinner,sun4i-a10-ve-clk.yaml | 51 clocks = <&pll4>;
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| H A D | allwinner,sun9i-a80-ahb-clk.yaml | 48 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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| H A D | allwinner,sun9i-a80-cpus-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
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| H A D | allwinner,sun9i-a80-gt-clk.yaml | 48 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
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| H A D | qcom,gcc-mdm9615.yaml | 31 - description: PLL4 from LLC
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| H A D | allwinner,sun4i-a10-mmc-clk.yaml | 82 clocks = <&osc24M>, <&pll4>;
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| H A D | qcom,gcc-apq8064.yaml | 48 - const: pll4
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | ti,j721e-cpb-audio.yaml | 19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
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| H A D | ti,j721e-cpb-ivi-audio.yaml | 24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
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| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx6_ssi.c | 137 uint32_t mfi; /* PLL4 Multiplication Factor Integer */
138 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
139 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
144 { 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */
157 * PLL4 div select -/ | | | | | | | | |
158 * PLL4 num --------------/ | | | | | | | |
159 * PLL4 denom -------------------/ | | | | | | |
160 * PLL4 post div ---------------------/ | | | | | |
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| H A D | imx6_ccm.c | 220 * Select PLL4 (Audio PLL) clock multiplexer as source. in imx_ccm_ssi_configure()
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| /freebsd/sys/arm/freescale/vybrid/ |
| H A D | vf_anadig.c | 61 #define ANADIG_PLL4_CTRL 0x070 /* PLL4 Control */
62 #define ANADIG_PLL4_NUM 0x080 /* PLL4 Numerator */
63 #define ANADIG_PLL4_DENOM 0x090 /* PLL4 Denominator */
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| H A D | vf_ccm.c | 178 PLL4 clock divider (before switching the clocks should be gated)
210 .sel_val = 0x3, /* Divided PLL4 main clock */
314 .sel_val = 0x3, /* Divided PLL4 main clock */
324 {"pll4", &pll4_clk},
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| H A D | vf_sai.c | 111 uint32_t mfi; /* PLL4 Multiplication Factor Integer */
112 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
113 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | qcom,lcc-ipq806x.h | 9 #define PLL4 0 macro
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| H A D | qcom,lcc-msm8960.h | 9 #define PLL4 0 macro
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| H A D | qcom,lcc-mdm9615.h | 11 #define PLL4 0 macro
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| H A D | stm32mp13-clks.h | 22 #define PLL4 9 macro
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| H A D | stm32mp1-clks.h | 186 #define PLL4 179 macro
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stm32mp157c-odyssey.dts | 41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
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| /freebsd/sys/contrib/device-tree/src/arm/qcom/ |
| H A D | qcom-msm8960.dtsi | 136 <&lcc PLL4>;
137 clock-names = "cxo", "pxo", "pll4";
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| H A D | qcom-mdm9615.dtsi | 108 <&lcc PLL4>;
|