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/linux/drivers/clk/sunxi/
H A Dclk-a10-pll2.c16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup()
73 /* Setup the gate part of the PLL2 */ in sun4i_pll2_setup()
82 /* Setup the multiplier part of the PLL2 */ in sun4i_pll2_setup()
95 base_clk = clk_register_composite(NULL, "pll2-base", in sun4i_pll2_setup()
109 * PLL2-1x in sun4i_pll2_setup()
130 * PLL2-2x in sun4i_pll2_setup()
133 * a fixed divider from the PLL2 base clock. in sun4i_pll2_setup()
143 /* PLL2-4x */ in sun4i_pll2_setup()
152 /* PLL2-8x */ in sun4i_pll2_setup()
[all …]
H A DMakefile12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
/linux/include/linux/iio/frequency/
H A Dad9523.h126 * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
127 * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
128 * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
129 * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
130 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
133 * @rpole2: PLL2 loop filter Rpole resistor value.
134 * @rzero: PLL2 loop filter Rzero resistor value.
135 * @cpole1: PLL2 loop filter Cpole capacitor value.
136 * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
172 /* PLL2 Setting */
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-mod1-clk.yaml44 #include <dt-bindings/clock/sun4i-a10-pll2.h>
50 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
51 <&pll2 SUN4I_A10_PLL2_4X>,
52 <&pll2 SUN4I_A10_PLL2_2X>,
53 <&pll2 SUN4I_A10_PLL2_1X>;
H A Dstarfive,jh7110-syscrg.yaml32 - description: PLL2
46 - description: PLL2
H A Drenesas,cpg-clocks.yaml80 - const: pll2
206 - const: pll2
H A Dimx28-clock.yaml22 pll2 3
H A Drenesas,cpg-div6-clock.yaml60 clock-output-names = "main", "pll0", "pll1", "pll2",
/linux/sound/soc/codecs/
H A Dak4642.c114 #define PLL2 (1 << 6) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
345 pll = PLL2; in ak4642_dai_set_sysclk()
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
H A Dadav80x.c207 SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0),
223 clk = "PLL2"; in adav80x_dapm_sysclk_check()
270 { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check },
273 { "PLL2", NULL, "OSC", adav80x_dapm_pll_check },
610 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2"); in adav80x_set_sysclk()
612 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2"); in adav80x_set_sysclk()
810 snd_soc_dapm_force_enable_pin(dapm, "PLL2"); in adav80x_probe()
/linux/drivers/mfd/
H A Dsm501.c116 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
/linux/drivers/clk/mmp/
H A Dclk-of-mmp2.c107 {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
112 …{MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000…
127 {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
131 {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
300 static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
311 static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
318 … * const mmp2_gpu_gc_parent_names[] = {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"};
320 static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2", "pll2_2", "usb_pll"};
323 static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"};
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/linux/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
293 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
300 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
316 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
323 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/linux/drivers/media/i2c/
H A Dsaa711x_regs.h181 /* second PLL (PLL2) and Pulsegenerator Programming */
535 /* second PLL (PLL2) and Pulsegenerator Programming */
541 "Nominal PLL2 DTO"},
543 "PLL2 Increment"},
545 "PLL2 Status"},
558 "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
/linux/drivers/clk/mxs/
H A Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); in mx28_clocks_init()
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi196 * that is parent of TIMCLK, PLL1 and PLL2
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
242 pll2: pll2@0 { label
253 clocks = <&pll2>;
268 clocks = <&pll2>;
276 clocks = <&pll2>;
/linux/drivers/clk/
H A Dclk-lmk04832.c143 /* 0x160 - 0x16e PLL2 Configuration */
241 * @oscin: PLL2 input clock
442 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
444 * @prate: parent rate to the PLL2, usually OSCin
508 dev_err(lmk->dev, "PLL2 parameters out of range\n"); in lmk04832_vco_round_rate()
539 dev_err(lmk->dev, "failed to determine PLL2 parameters\n"); in lmk04832_vco_set_rate()
561 * PLL2_N registers must be programmed after other PLL2 dividers are in lmk04832_vco_set_rate()
588 * path in PLL2 single loop mode.
773 * PLL2-only use case, this will be complete in less than one SPI in lmk04832_sclk_sync_sequence()
H A Dclk-k210.c265 #define K210_PLL_SEL GENMASK(27, 26) /* PLL2 only */
588 /* PLL2 has IN0, PLL0 and PLL1 as parents */ in k210_register_plls()
589 ret = k210_register_pll(np, ksc, K210_PLL2, "pll2", 3, &k210_pll2_ops); in k210_register_plls()
591 pr_err("%pOFP: register PLL2 failed\n", np); in k210_register_plls()
948 /* Clocks with PLL2 as source */ in k210_clk_init()
/linux/drivers/gpu/drm/tegra/
H A Dsor.c369 unsigned int pll2; member
1453 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1463 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
2285 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2300 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2302 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2306 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dmediatek,mt8188-afe.yaml49 - description: audio pll2 clock
66 - description: audio pll2 divide 4
/linux/include/soc/canaan/
H A Dk210-sysctl.h17 #define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */
/linux/drivers/clk/renesas/
H A Dr8a779f0-cpg-mssr.c62 DEF_GEN4_PLL_V9_24(".pll2", 2, CLK_PLL2, CLK_MAIN),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,dra7-dss.txt24 'pll1', 'pll2_clkctrl', 'pll2'

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