Searched full:pll15 (Results 1 – 4 of 4) sorted by relevance
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!38 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via29 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
207 clk_id == J721E_CLK_PARENT_48000 ? "PLL4" : "PLL15", in j721e_configure_refclk()519 [J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */528 [J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */
280 { .fc_id = 254, .cpu_id = 119, .valid = 1, .name = "PLL15" },