| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | allwinner,sun4i-a10-pll1-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
47 compatible = "allwinner,sun4i-a10-pll1-clk";
56 compatible = "allwinner,sun6i-a31-pll1-clk";
59 clock-output-names = "pll1";
65 compatible = "allwinner,sun8i-a23-pll1-clk";
68 clock-output-names = "pll1";
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| H A D | qoriq-clock.txt | 168 pll1: pll1@820 {
173 clock-output-names = "pll1", "pll1-div2";
180 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
181 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
189 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
190 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| H A D | microchip,mpfs-ccc.yaml | 25 - description: PLL1's control registers
37 - description: PLL1's refclk0
38 - description: PLL1's refclk1
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| H A D | renesas,r8a73a4-cpg-clocks.txt | 17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
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| H A D | renesas,sh73a0-cpg-clocks.txt | 19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
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| H A D | silabs,si5351.txt | 82 /* connect xtal input as source of pll0 and pll1 */
105 * - pll1 as clock source of multisynth1
107 * - multisynth1 can change pll1
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| H A D | renesas,cpg-clocks.yaml | 75 - const: pll1
201 - const: pll1
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| H A D | allwinner,sun4i-a10-cpu-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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| H A D | prima2-clock.txt | 17 pll1 2
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| H A D | imx28-clock.yaml | 21 pll1 2
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| H A D | renesas,cpg-div6-clock.yaml | 60 clock-output-names = "main", "pll0", "pll1", "pll2",
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| H A D | ti,cdce925.txt | 30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
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| H A D | st,nomadik.txt | 30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/davinci/ |
| H A D | pll.txt | 10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
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| /freebsd/sys/contrib/device-tree/Bindings/clock/st/ |
| H A D | st,clkgen-pll.txt | 15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
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| /freebsd/sys/arm/freescale/vybrid/ |
| H A D | vf_anadig.c | 76 #define ANADIG_PLL1_CTRL 0x270 /* PLL1 Control */
77 #define ANADIG_PLL1_SS 0x280 /* PLL1 Spread Spectrum */
78 #define ANADIG_PLL1_NUM 0x290 /* PLL1 Numerator */
79 #define ANADIG_PLL1_DENOM 0x2A0 /* PLL1 Denominator */
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stih410-clock.dtsi | 101 clk_s_c0_pll1: clk-s-c0-pll1 {
103 compatible = "st,clkgen-pll1-c0";
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| H A D | stih418-clock.dtsi | 101 clk_s_c0_pll1: clk-s-c0-pll1 {
103 compatible = "st,clkgen-pll1-c0";
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| H A D | stih407-clock.dtsi | 96 clk_s_c0_pll1: clk-s-c0-pll1 {
98 compatible = "st,clkgen-pll1-c0";
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| H A D | ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
219 pll1: pll1@0 { label
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
230 clocks = <&pll1>;
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | mediatek,mt8188-afe.yaml | 48 - description: audio pll1 clock
65 - description: audio pll1 divide 4
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | imx8mq-clock.h | 42 /* AUDIO PLL1 */
56 /* VIDEO PLL1 */
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| H A D | qcom,mmcc-msm8960.h | 126 #define PLL1 117 macro
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| /freebsd/sys/arm/nvidia/drm2/ |
| H A D | tegra_hdmi.c | 130 uint32_t pll1; member
142 .pll1 = 0x00301B00,
151 .pll1 = 0x00301500,
160 .pll1 = 0x00301500,
169 .pll1 = 0x00300F00,
651 WR4(sc, HDMI_NV_PDISP_SOR_PLL1, tmds->pll1); in tmds_init()
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| /freebsd/sys/contrib/device-tree/Bindings/display/ti/ |
| H A D | ti,dra7-dss.txt | 24 'pll1', 'pll2_clkctrl', 'pll2'
|