| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/davinci/ |
| H A D | pll.txt | 9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | qoriq-clock.txt | 160 pll0: pll0@800 {
165 clock-output-names = "pll0", "pll0-div2";
180 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
181 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
189 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
190 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| H A D | microchip,mpfs-ccc.yaml | 24 - description: PLL0's control registers
35 - description: PLL0's refclk0
36 - description: PLL0's refclk1
|
| H A D | renesas,r8a73a4-cpg-clocks.txt | 17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
|
| H A D | renesas,sh73a0-cpg-clocks.txt | 19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
|
| H A D | silabs,si5351.txt | 82 /* connect xtal input as source of pll0 and pll1 */
88 * - pll0 as clock source of multisynth0
90 * - multisynth0 can change pll0
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| H A D | renesas,cpg-clocks.yaml | 74 - const: pll0
200 - const: pll0
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| H A D | imx28-clock.yaml | 20 pll0 1
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| H A D | renesas,cpg-div6-clock.yaml | 60 clock-output-names = "main", "pll0", "pll1", "pll2",
|
| /freebsd/sys/contrib/device-tree/Bindings/clock/st/ |
| H A D | st,clkgen-pll.txt | 12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
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| H A D | st,clkgen.txt | 51 compatible = "st,clkgen-pll0";
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| /freebsd/sys/contrib/device-tree/src/arc/ |
| H A D | abilis_tb10x.dtsi | 48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
|
| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stih410-clock.dtsi | 75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
|
| H A D | stih418-clock.dtsi | 75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
|
| H A D | stih407-clock.dtsi | 70 compatible = "st,clkgen-pll0-a0";
89 clk_s_c0_pll0: clk-s-c0-pll0 {
91 compatible = "st,clkgen-pll0-c0";
|
| /freebsd/sys/arm/mv/ |
| H A D | mv_cp110_clock.c | 60 static const char *clk_parents_0[] = {"cp110-pll0-0"};
61 static const char *clk_parents_1[] = {"cp110-pll0-1"};
210 pll0_name = mv_cp110_clock_name(dev, "cp110-pll0"); in mv_cp110_clock_attach()
|
| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | intel,keembay-display.yaml | 28 - description: pll0 clock
|
| /freebsd/sys/arm/nvidia/drm2/ |
| H A D | tegra_hdmi.c | 129 uint32_t pll0; member
141 .pll0 = 0x01003010,
150 .pll0 = 0x01003110,
159 .pll0 = 0x01003310,
168 .pll0 = 0x01003F10,
650 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, tmds->pll0); in tmds_init()
|
| /freebsd/sys/dev/bhnd/cores/pmu/ |
| H A D | bhnd_pmu_subr.c | 69 static uint32_t bhnd_pmu5_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m);
71 static uint32_t bhnd_pmu6_4706_clock(struct bhnd_pmu_query *sc, u_int pll0,
2216 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
2219 bhnd_pmu5_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m) in bhnd_pmu5_clock() argument
2227 if ((pll0 & 3) || (pll0 > BHND_PMU4716_MAINPLL_PLL0)) { in bhnd_pmu5_clock()
2228 PMU_LOG(sc, "%s: Bad pll0: %d", __func__, pll0); in bhnd_pmu5_clock()
2249 pll0 + BHND_PMU5_PLL_P1P2_OFF); in bhnd_pmu5_clock()
2258 pll0 + BHND_PMU5_PLL_M14_OFF); in bhnd_pmu5_clock()
2267 pll0 + BHND_PMU5_PLL_NM5_OFF); in bhnd_pmu5_clock()
2285 bhnd_pmu6_4706_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m) in bhnd_pmu6_4706_clock() argument
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | dove-cubox.dts | 101 /* connect xtal input as source of pll0 and pll1 */
|
| /freebsd/sys/contrib/device-tree/src/mips/ingenic/ |
| H A D | gcw0.dts | 443 * PLL0 frequency on demand without having to suspend peripherals.
446 * Put the GPU under PLL0 since we want a higher frequency.
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | qcom,gcc-ipq806x.h | 229 #define PLL0 220 macro
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| H A D | qcom,gcc-msm8660.h | 256 #define PLL0 247 macro
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| H A D | qcom,gcc-mdm9615.h | 286 #define PLL0 276 macro
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| H A D | qcom,gcc-msm8960.h | 284 #define PLL0 276 macro
|