| /freebsd/sys/contrib/device-tree/Bindings/c6x/ |
| H A D | clocks.txt | 1 C6X PLL Clock Controllers
10 - compatible: "ti,c64x+pll"
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | keystone-pll.txt | 1 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
4 PLL is controlled by a PLL controller registers along with memory mapped
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
15 - reg - pll control0 and pll multiplier registers
17 post-divider registers are applicable only for main pll clock
24 compatible = "ti,keystone,main-pll-clock";
33 compatible = "ti,keystone,pll-clock";
35 clock-output-names = "pa-pll-clk";
42 - compatible : shall be "ti,keystone,pll-mux-clock"
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| H A D | qoriq-clock.txt | 5 multiple phase locked loops (PLL) to create a variety of frequencies
70 platform PLL.
88 4 platform pll n=pll/(n+1). For example, when n=1,
117 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
118 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
125 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
126 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
129 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
130 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
132 * 0 - equal to the PLL frequency
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| H A D | qca,ath79-pll.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
6 - compatible: has to be "qca,<soctype>-pll" and one of the following
8 - "qca,ar7100-pll"
9 - "qca,ar7240-pll"
10 - "qca,ar9130-pll"
11 - "qca,ar9330-pll"
12 - "qca,ar9340-pll"
13 - "qca,qca9550-pll"
24 pll-controller@18050000 {
25 compatible = "qca,ar9132-pll", "qca,ar9130-pll";
|
| H A D | qcom,mmcc.yaml | 83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
89 - description: HDMI phy PLL clock
149 - description: HDMI phy PLL clock
150 - description: eDP phy PLL link clock
151 - description: eDP phy PLL vco clock
188 - description: HDMI phy PLL clock
189 - description: eDP phy PLL link clock
190 - description: eDP phy PLL vco clock
232 - description: Global PLL
[all...] |
| H A D | vt8500.txt | 9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
16 - reg : shall be the control register offset from PMC base for the pll clock.
23 be a pll output.
61 compatible = "wm,wm8650-pll-clock";
|
| H A D | brcm,iproc-clocks.txt | 8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
14 Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
22 clock control registers required for the PLL
25 The input parent clock phandle for the PLL. For most iProc PLLs, this is an
89 PLL and leaf clock compatible strings for Cygnus are:
97 The following table defines the set of PLL/clock index and ID for Cygnus.
142 PLL and leaf clock compatible strings for Hurricane 2 are:
145 The following table defines the set of PLL/clock for Hurricane 2:
[all …]
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| H A D | fsl,qoriq-clock-legacy.yaml | 22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
28 - fsl,qoriq-platform-pll-1.0
29 - fsl,qoriq-platform-pll-2.0
74 - fsl,qoriq-core-pll-1.0
75 - fsl,qoriq-core-pll-2.0
81 * 0 - equal to the PLL frequency
82 * 1 - equal to the PLL frequency divided by 2
83 * 2 - equal to the PLL frequency divided by 4
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| H A D | sophgo,sg2042-pll.yaml | 4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
7 title: Sophgo SG2042 PLL Clock Generator
14 const: sophgo,sg2042-pll
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
34 See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
48 compatible = "sophgo,sg2042-pll";
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| H A D | silabs,si5351.txt | 30 - silabs,pll-source: pair of (number, source) for each pll. Allows
31 to overwrite clock source of pll A (number=0) or B (number=1).
49 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
51 - silabs,pll-master: boolean, multisynth can change pll frequency.
52 - silabs,pll-reset: boolean, clock output can reset its pll.
83 silabs,pll-source = <0 0>, <1 0>;
98 silabs,pll-master;
114 pll-master;
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| H A D | snps,hsdk-pll-clock.txt | 1 Binding for the HSDK Generic PLL clock
8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
13 - clocks: shall be the input parent clock phandle for the PLL.
24 compatible = "snps,hsdk-core-pll-clock";
|
| H A D | snps,pll-clock.txt | 1 Binding for the AXS10X Generic PLL clock
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
24 compatible = "snps,axs10x-arc-pll-clock";
|
| H A D | baikal,bt1-ccu-pll.yaml | 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
52 with an interface wrapper (so called safe PLL' clocks switcher) to simplify
53 the PLL configuration procedure. The PLLs work as depicted on the next
71 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
73 the binding supports the PLL dividers configuration in accordance with a
81 The CCU PLL dts-node uses the common clock bindings with no custom
83 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
89 const: baikal,bt1-ccu-pll
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| H A D | xgene.txt | 9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
16 Required properties for SoC or PCP PLL clocks:
17 - reg : shall be the physical PLL register address for the pll clock.
21 - clock-output-names : shall be the name of the PLL referenced by derive
23 Optional properties for PLL clocks:
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
32 Optional properties for PLL clocks:
|
| H A D | fsl,qoriq-clock.yaml | 15 multiple phase locked loops (PLL) to create a variety of frequencies
92 4 platform pll n=pll/(n+1). For example, when n=1,
107 platform PLL.
124 '^pll[0-9]@[a-f0-9]+$':
128 '^platform\-pll@[a-f0-9]+$':
167 compatible = "fsl,qoriq-core-pll-1.0";
175 compatible = "fsl,qoriq-core-pll-1.0";
200 platform-pll@c00 {
203 compatible = "fsl,qoriq-platform-pll-1.0";
205 clock-output-names = "platform-pll", "platform-pll-div2";
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| H A D | amlogic,c3-pll-clkc.yaml | 5 $id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
8 title: Amlogic C3 series PLL Clock Controller
18 const: amlogic,c3-pll-clkc
25 - description: input top pll
26 - description: input mclk pll
27 - description: input fix pll
54 compatible = "amlogic,c3-pll-clkc";
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| H A D | amlogic,a1-peripherals-clkc.yaml | 27 - description: input fixed pll div2
28 - description: input fixed pll div3
29 - description: input fixed pll div5
30 - description: input fixed pll div7
31 - description: input hifi pll
33 - description: input sys pll
58 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
|
| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | ti,pcm512x.yaml | 38 absent the device will be configured to clock from BCLK. If pll-in and
39 pll-out are specified in addition to a clock, the device is configured to
45 pll-in:
46 description: GPIO pin used to connect the pll using <1> through <6>. The
47 device will be configured for clock input on the given pll-in pin.
52 pll-out:
53 description: GPIO pin used to connect the pll using <1> through <6>. The
54 device will be configured for PLL output on the given pll-out pin. An
55 external connection from the pll-out pin to the SCLK pin is assumed.
77 pll-in:
[all …]
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| H A D | pcm512x.txt | 20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
51 pll-in = <3>;
52 pll-out = <6>;
|
| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | nvidia,tegra124-xusb.txt | 49 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
50 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
51 - avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
53 - hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
59 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
60 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
61 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
62 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
127 avdd-pll-utmip-supply = <&vddio_1v8>;
128 avdd-pll-erefe-supply = <&avdd_1v05_run>;
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| H A D | nvidia,tegra124-xusb.yaml | 55 - description: USB PLL
57 - description: I/O PLL
117 avdd-pll-utmip-supply:
118 description: UTMI PLL power supply. Must supply 1.8 V.
120 avdd-pll-erefe-supply:
121 description: PLLE reference PLL power supply. Must supply 1.05 V.
123 avdd-usb-ss-pll-supply:
124 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
129 hvdd-usb-ss-pll-e-supply:
195 avdd-pll-utmip-supply = <&vddio_1v8>;
[all …]
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| H A D | nvidia,tegra210-xusb.yaml | 47 - description: USB PLL
49 - description: I/O PLL
120 avdd-pll-utmip-supply:
121 description: UTMI PLL power supply. Must supply 1.8 V.
123 avdd-pll-uerefe-supply:
124 description: PLLE reference PLL power supply. Must supply 1.05 V.
126 dvdd-usb-ss-pll-supply:
127 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
129 hvdd-usb-ss-pll-e-supply:
183 avdd-pll-utmip-supply = <&vdd_1v8>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | allwinner,sun4i-a10-hdmi.yaml | 38 - description: The first video PLL
39 - description: The second video PLL
45 - description: The first video PLL
46 - description: The second video PLL
53 - const: pll-0
54 - const: pll-1
60 - const: pll-0
61 - const: pll-1
138 clock-names = "ahb", "mod", "pll-0", "pll-1";
|
| /freebsd/sys/dev/clk/allwinner/ |
| H A D | ccu_a13.c | 138 CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll-ddr", 0x100, 0)
139 CCU_GATE(CLK_DRAM_CSI, "dram-csi", "pll-ddr", 0x100, 1)
140 CCU_GATE(CLK_DRAM_DE_FE, "dram-de-fe", "pll-ddr", 0x100, 25)
141 CCU_GATE(CLK_DRAM_DE_BE, "dram-de-be", "pll-ddr", 0x100, 26)
142 CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll-ddr", 0x100, 29)
143 CCU_GATE(CLK_DRAM_IEP, "dram-iep", "pll-ddr", 0x100, 31)
145 CCU_GATE(CLK_CODEC, "codec", "pll-audio", 0x140, 31)
154 .name = "pll-core",
168 * We only implement pll-audio for now
169 * For pll-audio-2/4/8 x we need a way to change the frequency
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| /freebsd/sys/dev/firmware/xilinx/ |
| H A D | pm_defs.h | 117 /* PLL control API functions */
325 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL
326 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL
327 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL
328 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input
329 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode
332 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control
333 * @PM_PLL_PARAM_CP: PLL charge pump control
334 * @PM_PLL_PARAM_RES: PLL loop filter resistor control
351 * @PM_PLL_MODE_RESET: PLL is in reset (not locked)
[all …]
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