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/linux/drivers/pinctrl/
H A Dpinctrl-single.c205 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
206 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
207 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
268 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs, in pcs_pin_reg_offset_get() argument
271 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
273 if (pcs->bits_per_mux) { in pcs_pin_reg_offset_get()
276 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
283 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs, in pcs_pin_shift_reg_get() argument
286 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; in pcs_pin_shift_reg_get()
293 struct pcs_device *pcs; in pcs_pin_dbg_show() local
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/linux/drivers/net/pcs/
H A Dpcs-lynx.c3 * Lynx PCS MDIO helpers
8 #include <linux/pcs-lynx.h>
11 #define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */
24 struct phylink_pcs pcs; member
35 #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
36 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
38 static unsigned int lynx_pcs_inband_caps(struct phylink_pcs *pcs, in lynx_pcs_inband_caps() argument
60 static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, in lynx_pcs_get_state_usxgmii() argument
63 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
64 int addr = pcs->addr; in lynx_pcs_get_state_usxgmii()
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H A Dpcs-mtk-lynxi.c13 #include <linux/pcs/pcs-mtk-lynxi.h>
74 * @dev: Pointer to device owning the PCS
77 * @pcs: Phylink PCS structure
84 struct phylink_pcs pcs; member
89 static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs) in pcs_to_mtk_pcs_lynxi() argument
91 return container_of(pcs, struct mtk_pcs_lynxi, pcs); in pcs_to_mtk_pcs_lynxi()
94 static unsigned int mtk_pcs_lynxi_inband_caps(struct phylink_pcs *pcs, in mtk_pcs_lynxi_inband_caps() argument
108 static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs, in mtk_pcs_lynxi_get_state() argument
112 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); in mtk_pcs_lynxi_get_state()
141 pcs_fwnode = fwnode_get_named_child_node(fwnode, "pcs"); in mtk_pcs_config_polarity()
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H A DMakefile2 # Makefile for Linux PCS drivers
4 pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
5 pcs-xpcs-nxp.o pcs-xpcs-wx.o
8 obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
9 obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
10 obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
H A Dpcs-xpcs.c11 #include <linux/pcs/pcs-xpcs.h>
17 #include "pcs-xpcs.h"
20 container_of((pl_pcs), struct dw_xpcs, pcs)
181 return &xpcs->pcs; in xpcs_to_phylink_pcs()
604 * PCS link will bounce. To avoid reporting link up too soon we include in xpcs_resolve_pma()
645 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, in xpcs_validate() argument
653 xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_validate()
670 static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, in xpcs_inband_caps() argument
673 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); in xpcs_inband_caps()
721 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) in xpcs_pre_config() argument
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H A Dpcs-rzn1-miic.c17 #include <linux/pcs-rzn1-miic.h>
23 #include <dt-bindings/net/pcs-rzn1-miic.h>
24 #include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
255 * @pcs: PCS structure associated to the port
261 struct phylink_pcs pcs; member
266 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) in phylink_pcs_to_miic_port() argument
268 return container_of(pcs, struct miic_port, pcs); in phylink_pcs_to_miic_port()
335 static int miic_config(struct phylink_pcs *pcs, unsigne in miic_config()
332 miic_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit) miic_config() argument
383 miic_link_up(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex) miic_link_up() argument
417 miic_pre_init(struct phylink_pcs * pcs) miic_pre_init() argument
511 miic_destroy(struct phylink_pcs * pcs) miic_destroy() argument
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/linux/include/linux/
H A Dphylink.h27 /* PCS "negotiation" mode.
153 * are supported by the MAC/PCS.
192 * @mac_select_pcs: Select a PCS for the interface mode.
243 * mac_select_pcs: Select a PCS for the interface mode.
245 * @interface: PHY interface mode for PCS
250 * This must not modify any state. It is used to query which PCS should
253 * set the PCS that will be used.
302 * the results of in-band negotiation/status from the MAC PCS should be used
365 * complete any necessary steps after the MAC and PCS have been configured
413 * where these settings are not automatically conveyed from the PCS block,
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/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c3 * Marvell 88E6352 family SERDES PCS support
130 static struct mv88e639x_pcs *sgmii_pcs_to_mv88e639x_pcs(struct phylink_pcs *pcs) in sgmii_pcs_to_mv88e639x_pcs() argument
132 return container_of(pcs, struct mv88e639x_pcs, sgmii_pcs); in sgmii_pcs_to_mv88e639x_pcs()
184 static int mv88e639x_sgmii_pcs_enable(struct phylink_pcs *pcs) in mv88e639x_sgmii_pcs_enable() argument
186 struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs); in mv88e639x_sgmii_pcs_enable()
194 static void mv88e639x_sgmii_pcs_disable(struct phylink_pcs *pcs) in mv88e639x_sgmii_pcs_disable() argument
196 struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs); in mv88e639x_sgmii_pcs_disable()
202 static void mv88e639x_sgmii_pcs_pre_config(struct phylink_pcs *pcs, in mv88e639x_sgmii_pcs_pre_config() argument
205 struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs); in mv88e639x_sgmii_pcs_pre_config()
241 static int mv88e639x_sgmii_pcs_post_config(struct phylink_pcs *pcs, in mv88e639x_sgmii_pcs_post_config() argument
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H A Dpcs-6352.c3 * Marvell 88E6352 family SERDES PCS support
33 static struct marvell_c22_pcs *pcs_to_marvell_c22_pcs(struct phylink_pcs *pcs) in pcs_to_marvell_c22_pcs() argument
35 return container_of(pcs, struct marvell_c22_pcs, phylink_pcs); in pcs_to_marvell_c22_pcs()
140 static int marvell_c22_pcs_enable(struct phylink_pcs *pcs) in marvell_c22_pcs_enable() argument
142 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs); in marvell_c22_pcs_enable()
152 static void marvell_c22_pcs_disable(struct phylink_pcs *pcs) in marvell_c22_pcs_disable() argument
154 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs); in marvell_c22_pcs_disable()
160 static void marvell_c22_pcs_get_state(struct phylink_pcs *pcs, in marvell_c22_pcs_get_state() argument
164 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs); in marvell_c22_pcs_get_state()
185 static int marvell_c22_pcs_config(struct phylink_pcs *pcs, in marvell_c22_pcs_config() argument
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H A Dpcs-6185.c3 * Marvell 88E6185 family SERDES PCS support
24 static struct mv88e6185_pcs *pcs_to_mv88e6185_pcs(struct phylink_pcs *pcs) in pcs_to_mv88e6185_pcs() argument
26 return container_of(pcs, struct mv88e6185_pcs, phylink_pcs); in pcs_to_mv88e6185_pcs()
57 static void mv88e6185_pcs_get_state(struct phylink_pcs *pcs, in mv88e6185_pcs_get_state() argument
61 struct mv88e6185_pcs *mpcs = pcs_to_mv88e6185_pcs(pcs); in mv88e6185_pcs_get_state()
99 static int mv88e6185_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, in mv88e6185_pcs_config() argument
107 static void mv88e6185_pcs_an_restart(struct phylink_pcs *pcs) in mv88e6185_pcs_an_restart() argument
126 * have a PCS or not. in mv88e6185_pcs_init()
/linux/drivers/net/dsa/b53/
H A Db53_serdes.c20 static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs) in pcs_to_b53_pcs() argument
22 return container_of(pcs, struct b53_pcs, pcs); in pcs_to_b53_pcs()
68 static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int neg_mode, in b53_serdes_config() argument
73 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_config()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config()
89 static void b53_serdes_an_restart(struct phylink_pcs *pcs) in b53_serdes_an_restart() argument
91 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_an_restart()
92 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_an_restart()
102 static void b53_serdes_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, in b53_serdes_get_state() argument
105 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_get_state()
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046-post.dtsi27 pcs-handle = <&qsgmiib_pcs3>;
28 pcs-handle-names = "qsgmii";
42 pcs-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
43 pcs-handle-names = "sgmii", "qsgmii";
48 pcs-handle = <&pcsphy5>, <&pcsphy5>;
49 pcs-handle-names = "sgmii", "qsgmii";
57 pcs-handle = <&pcsphy7>, <&qsgmiib_pcs2>, <&pcsphy7>;
58 pcs-handle-names = "sgmii", "qsgmii", "xfi";
62 qsgmiib_pcs1: ethernet-pcs@1 {
63 compatible = "fsl,lynx-pcs";
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H A Dfsl-ls1043-post.dtsi27 pcs-handle-names = "qsgmii";
32 pcs-handle = <&pcsphy1>, <&qsgmiib_pcs1>;
33 pcs-handle-names = "sgmii", "qsgmii";
44 pcs-handle = <&pcsphy4>, <&qsgmiib_pcs2>;
45 pcs-handle-names = "sgmii", "qsgmii";
50 pcs-handle = <&pcsphy5>, <&qsgmiib_pcs3>;
51 pcs-handle-names = "sgmii", "qsgmii";
58 qsgmiib_pcs1: ethernet-pcs@1 {
59 compatible = "fsl,lynx-pcs";
63 qsgmiib_pcs2: ethernet-pcs@2 {
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H A Dtqmls1088a-mbls10xxa-mc.dtsi17 pcs-handle = <&pcs1>;
21 pcs-handle = <&pcs2>;
25 pcs-handle = <&pcs3_0>;
29 pcs-handle = <&pcs3_1>;
33 pcs-handle = <&pcs3_2>;
37 pcs-handle = <&pcs3_3>;
41 pcs-handle = <&pcs7_0>;
45 pcs-handle = <&pcs7_1>;
49 pcs-handle = <&pcs7_2>;
53 pcs-handle = <&pcs7_3>;
/linux/Documentation/networking/
H A Dsfp-phylink.rst219 should be used to configure the MAC when the MAC and PCS are not
249 10. Some Ethernet controllers work in pair with a PCS (Physical Coding Sublayer)
252 PCS whose operation is transparent, some other require dedicated PCS
254 provides a PCS abstraction through :c:type:`struct phylink_pcs <phylink_pcs>`.
256 Identify if your driver has one or more internal PCS blocks, and/or if
257 your controller can use an external PCS block that might be internally
260 If your controller doesn't have any internal PCS, you can go to step 11.
262 If your Ethernet controller contains one or several PCS blocks, create
263 one :c:type:`struct phylink_pcs <phylink_pcs>` instance per PCS block within
268 struct phylink_pcs pcs;
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp.h47 #include "phy-qcom-qmp-pcs-v2.h"
49 #include "phy-qcom-qmp-pcs-v3.h"
51 #include "phy-qcom-qmp-pcs-v4.h"
53 #include "phy-qcom-qmp-pcs-v4_20.h"
55 #include "phy-qcom-qmp-pcs-v5.h"
57 #include "phy-qcom-qmp-pcs-v5_20.h"
59 #include "phy-qcom-qmp-pcs-v6.h"
61 #include "phy-qcom-qmp-pcs-v6-n4.h"
63 #include "phy-qcom-qmp-pcs-v6_20.h"
65 #include "phy-qcom-qmp-pcs-v7.h"
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H A Dphy-qcom-qmp-ufs.c27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
32 #include "phy-qcom-qmp-pcs-ufs-v7.h"
47 /* PCS registers */
1144 u16 pcs; member
1152 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1159 const struct qmp_phy_init_tbl *pcs; member
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_xgmi.c110 {"XGMI PCS DataLossErr",
112 {"XGMI PCS TrainingErr",
114 {"XGMI PCS CRCErr",
116 {"XGMI PCS BERExceededErr",
118 {"XGMI PCS TxMetaDataErr",
120 {"XGMI PCS ReplayBufParityErr",
122 {"XGMI PCS DataParityErr",
124 {"XGMI PCS ReplayFifoOverflowErr",
126 {"XGMI PCS ReplayFifoUnderflowErr",
128 {"XGMI PCS ElasticFifoOverflowErr",
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/linux/drivers/net/phy/
H A Dphylink.c46 struct phylink_pcs *pcs; member
519 struct phylink_pcs *pcs = NULL; in phylink_validate_mac_and_pcs() local
523 /* Get the PCS for this interface mode */ in phylink_validate_mac_and_pcs()
525 pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface); in phylink_validate_mac_and_pcs()
526 if (IS_ERR(pcs)) in phylink_validate_mac_and_pcs()
527 return PTR_ERR(pcs); in phylink_validate_mac_and_pcs()
530 if (pcs) { in phylink_validate_mac_and_pcs()
531 /* The PCS, if present, must be setup before phylink_create() in phylink_validate_mac_and_pcs()
535 if (!pcs->ops) { in phylink_validate_mac_and_pcs()
536 phylink_err(pl, "interface %s: uninitialised PCS\n", in phylink_validate_mac_and_pcs()
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/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml49 - const: eee-pcs
50 - const: rx-pcs-input
51 - const: rx-pcs-m
52 - const: rx-pcs
53 - const: tx-pcs
61 - const: pcs
137 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
138 "rx-pcs", "tx-pcs";
141 reset-names = "mac", "pcs";
/linux/Documentation/devicetree/bindings/net/pcs/
H A Dfsl,lynx-pcs.yaml4 $id: http://devicetree.org/schemas/net/pcs/fsl,lynx-pcs.yaml#
7 title: NXP Lynx PCS
13 NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as
19 const: fsl,lynx-pcs
36 qsgmii_pcs1: ethernet-pcs@1 {
37 compatible = "fsl,lynx-pcs";
/linux/drivers/clocksource/
H A Dtimer-pistachio.c70 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clocksource_read_cycles() local
80 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
81 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles()
82 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles()
83 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles()
96 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_set_mode() local
99 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
105 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode()
110 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs); in pistachio_clksrc_enable() local
114 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable()
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c4 #include <linux/pcs/pcs-xpcs.h>
383 bus->name = "SJA1105 PCS MDIO bus"; in sja1105_mdiobus_pcs_register()
384 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-pcs", in sja1105_mdiobus_pcs_register()
403 struct phylink_pcs *pcs; in sja1105_mdiobus_pcs_register() local
412 pcs = xpcs_create_pcs_mdiodev(bus, port); in sja1105_mdiobus_pcs_register()
413 if (IS_ERR(pcs)) { in sja1105_mdiobus_pcs_register()
414 rc = PTR_ERR(pcs); in sja1105_mdiobus_pcs_register()
418 priv->pcs[port] = pcs; in sja1105_mdiobus_pcs_register()
427 if (priv->pcs[port]) { in sja1105_mdiobus_pcs_register()
428 xpcs_destroy_pcs(priv->pcs[port]); in sja1105_mdiobus_pcs_register()
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/linux/drivers/net/dsa/lantiq/
H A Dmxl-gsw1xx.c35 struct phylink_pcs pcs; member
129 static unsigned int gsw1xx_pcs_inband_caps(struct phylink_pcs *pcs, in gsw1xx_pcs_inband_caps() argument
135 static struct gsw1xx_priv *pcs_to_gsw1xx(struct phylink_pcs *pcs) in pcs_to_gsw1xx() argument
137 return container_of(pcs, struct gsw1xx_priv, pcs); in pcs_to_gsw1xx()
140 static int gsw1xx_pcs_enable(struct phylink_pcs *pcs) in gsw1xx_pcs_enable() argument
142 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs); in gsw1xx_pcs_enable()
149 static void gsw1xx_pcs_disable(struct phylink_pcs *pcs) in gsw1xx_pcs_disable() argument
151 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs); in gsw1xx_pcs_disable()
162 static void gsw1xx_pcs_get_state(struct phylink_pcs *pcs, in gsw1xx_pcs_get_state() argument
166 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs); in gsw1xx_pcs_get_state()
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/linux/tools/testing/selftests/bpf/
H A Djit_disasm_helpers.c30 __u32 pcs[MAX_LOCAL_LABELS]; member
47 * - if print_phase is true and ref_value is in labels->pcs, in lookup_symbol()
50 * in labels->pcs; in lookup_symbol()
54 if (labels->pcs[i] == ref_value) in lookup_symbol()
58 labels->pcs[labels->cnt++] = ref_value; in lookup_symbol()
133 qsort(labels.pcs, labels.cnt, sizeof(*labels.pcs), cmp_u32); in disasm_one_func()
153 label_pc = bsearch(&pc, labels.pcs, labels.cnt, sizeof(*labels.pcs), cmp_u32); in disasm_one_func()
157 label = labels.names[label_pc - labels.pcs]; in disasm_one_func()
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