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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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H A Dfsl,fman-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
19 - fsl,fman-xmdio
20 - fsl,fman-memac-mdio
22 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
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H A Dxilinx_axienet.txt2 --------------------------------------------------------
5 provides connectivity to an external ethernet PHY supporting different
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
29 - phy-handle : Should point to the external phy device if exists. Pointing
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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H A Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
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H A Dfsl,qoriq-mc-dpmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 pcs-handle:
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H A Dfsl-fman.txt5 - FMan Node
6 - FMan Port Node
7 - FMan MURAM Node
8 - FMan dTSEC/XGEC/mEMAC Node
9 - FMan IEEE 1588 Node
10 - FMan MDIO Node
11 - Example
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
23 - compatible
32 - cell-index
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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H A Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb
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H A Dqcom,msm8996-qmp-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qm
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H A Dqcom,qmp-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (USB)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq6018-qmp-usb3-phy
20 - qcom,ipq8074-qmp-usb3-phy
21 - qcom,msm8996-qmp-usb3-phy
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H A Dqcom,qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (UFS)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sc8180x-qmp-ufs-phy
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H A Dqcom,qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
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H A Dmediatek,mt7988-xfi-tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7988 XFI T-PHY
10 - Daniel Golle <daniel@makrotopia.org>
13 The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
14 used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
15 MediaTek's 10G-capabale MT7988 SoC.
20 const: mediatek,mt7988-xfi-tphy
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H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8MQ USB3 PHY
10 - Li Jun <jun.li@nxp.com>
15 - fsl,imx8mq-usb-phy
16 - fsl,imx8mp-usb-phy
21 "#phy-cells":
27 clock-names:
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H A Dqcom,msm8996-qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (UFS, MSM8996)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
17 qcom,sc8280xp-qmp-ufs-phy.yaml.
22 - qcom,msm8996-qmp-ufs-phy
23 - qcom,msm8998-qmp-ufs-phy
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H A Dqcom,qmp-usb3-dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Wesley Cheng <quic_wcheng@quicinc.com>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7280-qmp-usb3-dp-phy
18 - qcom,sc8180x-qmp-usb3-dp-phy
19 - qcom,sc8280xp-qmp-usb43dp-phy
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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5ps
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/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
402 /* [0x28] XAUI PCS configuration */
404 /* [0x2c] XAUI PCS status */
406 /* [0x30] RXAUI PCS configuration */
408 /* [0x34] RXAUI PCS status */
446 /* [0x0] PCS register file address */
448 /* [0x4] PCS register file data */
462 /* [0x20] KR PCS config */
464 /* [0x24] KR PCS status */
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/freebsd/sys/contrib/device-tree/Bindings/net/pcs/
H A Dsnps,dw-xpcs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Ethernet PCS
10 - Serge Semin <fancer.lancer@gmail.com>
16 controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
17 optionally synthesized with a vendor-specific interface connected to
18 Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in
19 general it can be used to communicate with any compatible PHY.
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pci
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/freebsd/sys/dev/e1000/
H A De1000_82575.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
121 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
134 switch (hw->mac.type) { in e1000_sgmii_uses_mdio_82575()
155 * e1000_init_phy_params_82575 - Initialize PHY function ptrs
160 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82575() local
166 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; in e1000_init_phy_params_82575()
167 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; in e1000_init_phy_params_82575()
169 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82575()
170 phy->type = e1000_phy_none; in e1000_init_phy_params_82575()
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