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/linux/drivers/clk/samsung/
H A Dclk-s3c64xx.c224 GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
334 ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"),
356 ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"),
H A Dclk-exynos7.c761 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-rockchip.yaml107 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
/linux/include/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h68 #define PCLK_SPI0 53 macro
H A Dexynos7-clk.h104 #define PCLK_SPI0 12 macro
H A Drk3188-cru-common.h80 #define PCLK_SPI0 328 macro
H A Drk3128-cru.h107 #define PCLK_SPI0 338 macro
H A Drk3228-cru.h106 #define PCLK_SPI0 338 macro
H A Drk3368-cru.h122 #define PCLK_SPI0 338 macro
H A Drk3308-cru.h186 #define PCLK_SPI0 207 macro
H A Drk3288-cru.h130 #define PCLK_SPI0 338 macro
H A Dpx30-cru.h164 #define PCLK_SPI0 341 macro
H A Drockchip,rv1126-cru.h50 #define PCLK_SPI0 37 macro
H A Drockchip,rk3576-cru.h169 #define PCLK_SPI0 151 macro
H A Drockchip,rk3588-cru.h161 #define PCLK_SPI0 146 macro
H A Drk3399-cru.h242 #define PCLK_SPI0 347 macro
H A Drk3568-cru.h401 #define PCLK_SPI0 337 macro
/linux/drivers/clk/rockchip/
H A Dclk-rk3128.c501 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
H A Dclk-rk3228.c607 GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
H A Dclk-rk3188.c520 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
H A Dclk-rk3368.c802 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
H A Dclk-rv1126.c331 GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
H A Dclk-rk3308.c875 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS),
H A Dclk-px30.c858 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS),
/linux/arch/arm/boot/dts/rockchip/
H A Drk3xxx.dtsi454 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;

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