Home
last modified time | relevance | path

Searched full:p0 (Results 1 – 25 of 288) sorted by relevance

12345678910>>...12

/linux/arch/hexagon/mm/
H A Dcopy_user_template.S19 p0 = cmp.gtu(bytes,#0) define
20 if (!p0.new) jump:nt .Ldone
26 p0 = bitsclr(r3,#7) define
27 if (!p0.new) jump:nt .Loop_not_aligned_8
52 p0 = bitsclr(r4,#7) define
53 if (p0.new) jump:nt .Lalign
56 p0 = bitsclr(r3,#3) define
57 if (!p0.new) jump:nt .Loop_not_aligned_4
82 p0 = bitsclr(r3,#1) define
83 if (!p0.new) jump:nt .Loop_not_aligned
[all …]
/linux/arch/hexagon/lib/
H A Dmemset.S29 p0 = cmp.eq(r2, #0) define
36 if p0 jumpr r31 /* count == 0, so return */
41 p0 = tstbit(r9, #0) define
58 p0 = tstbit(r9, #1) define
60 if !p0 jump 3f /* skip initial byte store */
71 p0 = tstbit(r9, #2) define
73 if !p0 jump 4f /* skip initial half store */
84 p0 = cmp.gtu(r2, #7) define
86 if !p0 jump 5f /* skip initial word store */
91 p0 = cmp.gtu(r2, #11) define
[all …]
H A Dmemcpy_likely_aligned.S10 p0 = bitsclr(r1,#7) define
11 p0 = bitsclr(r0,#7) define
12 if (p0.new) r5:4 = memd(r1)
13 if (p0.new) r7:6 = memd(r1+#8)
16 if (!p0) jump:nt .Lmemcpy_call
17 if (p0) r9:8 = memd(r1+#16)
18 if (p0) r11:10 = memd(r1+#24)
19 p0 = cmp.gtu(r2,#64) define
22 if (p0) jump:nt .Lmemcpy_call
23 if (!p0) memd(r0) = r5:4
[all …]
H A Ddivsi3.S10 p0 = cmp.gt(r0,#-1) define
15 p3 = xor(p0,p1)
18 p0 = cmp.gtu(r3,r2) define
26 r0 = mux(p0,#0,r0)
27 p0 = or(p0,p1) define
28 if (p0.new) jumpr:nt r31
35 p0 = cmp.gtu(r6,#4) define
39 if (!p0) r6 = #3
50 if (!p0.new) r0 = add(r0,r5)
51 if (!p0.new) r2 = sub(r2,r4)
[all …]
H A Dudivsi3.S13 p0 = cmp.gtu(r1,r0) define
19 if (p0) jumpr r31
28 p0 = cmp.gtu(r2,r1) define
29 if (!p0.new) r1 = sub(r1,r2)
30 if (!p0.new) r0 = add(r0,r3)
34 p0 = cmp.gtu(r2,r1) define
35 if (!p0.new) r0 = add(r0,r3)
H A Dumodsi3.S12 p0 = cmp.gtu(r1,r0) define
16 if (p0) jumpr r31
26 p0 = cmp.gtu(r2,r0) define
27 if (!p0.new) r0 = sub(r0,r2)
32 p0 = cmp.gtu(r2,r0) define
33 if (!p0.new) r0 = sub(r0,r1)
H A Dmodsi3.S17 p0 = cmp.gtu(r1,r2) define
21 if (p0) jumpr r31
32 p0 = cmp.gtu(r2,r0) define
33 if (!p0.new) r0 = sub(r0,r2)
38 p0 = cmp.gtu(r2,r0) define
39 if (!p0.new) r0 = sub(r0,r1)
/linux/arch/x86/include/asm/
H A Dxor_avx.h29 static void xor_avx_2(unsigned long bytes, unsigned long * __restrict p0, in xor_avx_2() argument
42 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_2()
44 "=m" (p0[i / sizeof(*p0)])); \ in xor_avx_2()
49 p0 = (unsigned long *)((uintptr_t)p0 + 512); in xor_avx_2()
56 static void xor_avx_3(unsigned long bytes, unsigned long * __restrict p0, in xor_avx_3() argument
72 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_3()
74 "=m" (p0[i / sizeof(*p0)])); \ in xor_avx_3()
79 p0 = (unsigned long *)((uintptr_t)p0 + 512); in xor_avx_3()
87 static void xor_avx_4(unsigned long bytes, unsigned long * __restrict p0, in xor_avx_4() argument
106 "m" (p0[i / sizeof(*p0)])); \ in xor_avx_4()
[all …]
/linux/arch/hexagon/include/asm/
H A Dbitops.h39 " { P0 = tstbit(R12,R11); R12 = clrbit(R12,R11); }\n" in test_and_clear_bit()
41 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_clear_bit()
44 : "r10", "r11", "r12", "p0", "p1", "memory" in test_and_clear_bit()
63 " { P0 = tstbit(R12,R11); R12 = setbit(R12,R11); }\n" in test_and_set_bit()
65 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_set_bit()
68 : "r10", "r11", "r12", "p0", "p1", "memory" in test_and_set_bit()
89 " { P0 = tstbit(R12,R11); R12 = togglebit(R12,R11); }\n" in test_and_change_bit()
91 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_change_bit()
94 : "r10", "r11", "r12", "p0", "p1", "memory" in test_and_change_bit()
173 "{P0 = tstbit(%1,%2); if (P0.new) %0 = #1; if (!P0.new) %0 = #0;}\n" in arch_test_bit()
[all …]
H A Dcmpxchg.h32 " memw_locked(%1,P0) = %2;\n" /* store into memory */ in __arch_xchg()
33 " if (!P0) jump 1b;\n" in __arch_xchg()
36 : "memory", "p0" in __arch_xchg()
63 " { P0 = cmp.eq(%0,%2);\n" \
64 " if (!P0.new) jump:nt 2f; }\n" \
65 " memw_locked(%1,p0) = %3;\n" \
66 " if (!P0) jump 1b;\n" \
70 : "memory", "p0" \
/linux/scripts/coccinelle/misc/
H A Dminmax.cocci172 for p0 in p:
173 coccilib.report.print_report(p0, "WARNING opportunity for max()")
179 for p0 in p:
180 coccilib.org.print_todo(p0, "WARNING opportunity for max()")
186 for p0 in p:
187 coccilib.report.print_report(p0, "WARNING opportunity for max()")
193 for p0 in p:
194 coccilib.org.print_todo(p0, "WARNING opportunity for max()")
200 for p0 in p:
201 coccilib.report.print_report(p0, "WARNIN
[all...]
H A Ddoubleinit.cocci19 position p0,p;
23 struct I s =@p0 { ..., .fld@p = E, ...};
27 position r.p0,p;
31 struct I s =@p0 { ..., .fld@p = E, ...};
34 p0 << r.p0;
41 cocci.print_main(fld,p0)
46 p0 << r.p0;
54 coccilib.report.print_report(p0[0],msg)
/linux/Documentation/devicetree/bindings/ata/
H A Dceva,ahci-1v84.yaml41 ceva,p0-cominit-params:
46 ceva,p0-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
53 ceva,p0-comwake-params:
58 ceva,p0-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
65 ceva,p0-burst-params:
70 ceva,p0-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
77 ceva,p0-retry-params:
82 ceva,p0-retry-params = /bits/ 16 <RIT RCT>;
153 - ceva,p0-cominit-params
154 - ceva,p0-comwake-params
[all …]
/linux/drivers/gpu/drm/omapdrm/
H A Dtcm.h52 struct tcm_pt p0; member
228 slice->p0.y != slice->p1.y && in tcm_slice()
229 (slice->p0.x || (slice->p1.x != slice->tcm->width - 1))) { in tcm_slice()
232 slice->p1.y = (slice->p0.x) ? slice->p0.y : slice->p1.y - 1; in tcm_slice()
234 parent->p0.x = 0; in tcm_slice()
235 parent->p0.y = slice->p1.y + 1; in tcm_slice()
249 area->p0.y <= area->p1.y && in tcm_area_is_valid()
250 /* 1D coordinate relationship + p0.x check */ in tcm_area_is_valid()
252 area->p0.x < area->tcm->width && in tcm_area_is_valid()
253 area->p0.x + area->p0.y * area->tcm->width <= in tcm_area_is_valid()
[all …]
H A Dtcm-sita.c163 area->p0.x = pos % tcm->width; in sita_reserve_1d()
164 area->p0.y = pos / tcm->width; in sita_reserve_1d()
185 area->p0.x = pos % tcm->width; in sita_reserve_2d()
186 area->p0.y = pos / tcm->width; in sita_reserve_2d()
187 area->p1.x = area->p0.x + w - 1; in sita_reserve_2d()
188 area->p1.y = area->p0.y + h - 1; in sita_reserve_2d()
205 pos = area->p0.x + area->p0.y * tcm->width; in sita_free()
207 w = area->p1.x - area->p0.x + 1; in sita_free()
208 h = area->p1.y - area->p0.y + 1; in sita_free()
/linux/drivers/scsi/qla4xxx/
H A Dql4_dbg.c106 offsetof(struct isp_reg, u2.isp4022.p0.ext_hw_conf), in qla4xxx_dump_registers()
107 readw(&ha->reg->u2.isp4022.p0.ext_hw_conf)); in qla4xxx_dump_registers()
109 offsetof(struct isp_reg, u2.isp4022.p0.port_ctrl), in qla4xxx_dump_registers()
110 readw(&ha->reg->u2.isp4022.p0.port_ctrl)); in qla4xxx_dump_registers()
112 offsetof(struct isp_reg, u2.isp4022.p0.port_status), in qla4xxx_dump_registers()
113 readw(&ha->reg->u2.isp4022.p0.port_status)); in qla4xxx_dump_registers()
115 (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_out), in qla4xxx_dump_registers()
116 readw(&ha->reg->u2.isp4022.p0.gp_out)); in qla4xxx_dump_registers()
118 (uint8_t) offsetof(struct isp_reg, u2.isp4022.p0.gp_in), in qla4xxx_dump_registers()
119 readw(&ha->reg->u2.isp4022.p0.gp_in)); in qla4xxx_dump_registers()
[all …]
/linux/tools/memory-model/litmus-tests/
H A Ddep+plain.litmus8 * The data stored to *z1 and *z2 by P0() originates from P0()'s
10 * conditional of P0()'s if-statement creates a control dependency
11 * from that READ_ONCE() to P0()'s WRITE_ONCE().
16 P0(int *x, int *y, int *z1, int *z2)
H A DREADME192 P0(int *x, int *y)
216 P0()'s WRITE_ONCE() is read by its first READ_ONCE(), which is a
217 reads-from link (rf) and internal to the P0() process. This is
223 P0()'s second access is a READ_ONCE(), as opposed to (for example)
226 P0()'s third access is also a READ_ONCE(), but to y rather than x.
227 This is related to P0()'s second access by program order ("po"),
229 The resulting descriptor is "PodRR". Because P0()'s third access is
232 A from-read ("fre") relation links P0()'s third to P1()'s first
237 The remainder of P1() is similar to P0(), which means we add
239 P0()'s first access, which is WRITE_ONCE(), so we add "Fre Once".
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
H A Ddml_top_mcache.c289 params->mcache_allocations[plane_index].shift_granularity.p0, &p0shift); in dml2_top_mcache_validate_admissability()
324 per_plane_pipe_mcache_regs->main.p0.mcache_id_first = MCACHE_ID_UNASSIGNED; in reset_mcache_allocations()
325 per_plane_pipe_mcache_regs->main.p0.mcache_id_second = MCACHE_ID_UNASSIGNED; in reset_mcache_allocations()
326 per_plane_pipe_mcache_regs->main.p0.split_location = SPLIT_LOCATION_UNDEFINED; in reset_mcache_allocations()
328 per_plane_pipe_mcache_regs->mall.p0.mcache_id_first = MCACHE_ID_UNASSIGNED; in reset_mcache_allocations()
329 per_plane_pipe_mcache_regs->mall.p0.mcache_id_second = MCACHE_ID_UNASSIGNED; in reset_mcache_allocations()
330 per_plane_pipe_mcache_regs->mall.p0.split_location = SPLIT_LOCATION_UNDEFINED; in reset_mcache_allocations()
358 // P0 always enabled in dml2_top_mcache_build_mcache_programming()
370 params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p0.mcache_id_first = in dml2_top_mcache_build_mcache_programming()
373 params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p0.mcache_id_first = in dml2_top_mcache_build_mcache_programming()
[all …]
/linux/tools/testing/selftests/cgroup/
H A Dtest_cpuset_prs.sh213 "C2-3:P1:S+ C3:P1 . . C3 P0 . . 0 A1:3,A2:3 A1:P1,A2:P0"
250 …" C0-3:S+ C1-3:S+ C2-3 . X2-3 X2-3:P2 . . 0 A1:0-1,A2:2-3,A3:2-3 A1:P0,A2:P2 2-…
251 " C0-3:S+ C1-3:S+ C2-3 . X2-3 X3:P2 . . 0 A1:0-2,A2:3,A3:3 A1:P0,A2:P2 3"
252 " C0-3:S+ C1-3:S+ C2-3 . X2-3 X2-3 X2-3:P2 . 0 A1:0-1,A2:1,A3:2-3 A1:P0,A3:P2 2-3"
253 " C0-3:S+ C1-3:S+ C2-3 . X2-3 X2-3 X2-3:P2:C3 . 0 A1:0-1,A2:1,A3:2-3 A1:P0,A3:P2 2-3"
254 …1-3:S+ C2-3 C2-3 . . . P2 0 A1:0-3,A2:1-3,A3:2-3,B1:2-3 A1:P0,A3:P0,B1:P-2"
265 A1:P0,A2:P1,A3:P2,B1:P1 2-3"
267 A1:P0,A2:P1,A3:P2,B1:P1 2-4,2-3"
269 A1:P0,A2:P1,A3:P0,B1:P1"
271 A1:P0,A2:P1,A3:P2,B1:P1 2-4,3"
[all …]
/linux/tools/memory-model/Documentation/
H A Dexplanation.txt116 P0()
132 Here the P0() function represents the interrupt handler running on one
135 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
163 instance, P1 might run entirely before P0 begins, in which case r1 and
164 r2 will both be 0 at the end. Or P0 might run entirely before P1
168 routines run concurrently. One possibility is that P1 runs after P0's
197 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
203 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
207 P0 stores 1 to buf before storing 1 to flag, since it executes
210 Since an instruction (in this case, P0's store to flag) cannot
[all …]
/linux/Documentation/scheduler/
H A Dsched-util-clamp.rst199 +- p0 +- p3 +- p4
279 p0->uclamp[UCLAMP_MIN] = 300
280 p0->uclamp[UCLAMP_MAX] = 900
285 then assuming both p0 and p1 are enqueued to the same rq, both UCLAMP_MIN
404 p0->uclamp[UCLAMP_MIN] = // system default;
405 p0->uclamp[UCLAMP_MAX] = // system default;
416 when p0 and p1 are attached to cgroup0, the values become:
420 p0->uclamp[UCLAMP_MIN] = cgroup0->cpu.uclamp.min = 20% * 1024;
421 p0->uclamp[UCLAMP_MAX] = cgroup0->cpu.uclamp.max = 60% * 1024;
426 when p0 and p1 are attached to cgroup1, these instead become:
[all …]
/linux/tools/testing/selftests/bpf/prog_tests/
H A Dsockmap_listen.c680 int c0, c1, p0, p1; in redir_to_connected() local
689 &p0, &p1); in redir_to_connected()
693 err = add_to_sockmap(sock_mapfd, p0, p1); in redir_to_connected()
720 xclose(p0); in redir_to_connected()
907 int c0 = -1, c1 = -1, p0 = -1, p1 = -1; in redir_partial() local
918 &p0, &p1); in redir_partial()
922 err = add_to_sockmap(sock_map, p0, p1); in redir_partial()
936 xclose(p0); in redir_partial()
1045 int s, c0, c1, p0, err; in test_reuseport_select_connected() local
1078 p0 = xaccept_nonblock(s, NULL, NULL); in test_reuseport_select_connected()
[all …]
/linux/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/
H A Duncore-cpa.json40 "BriefDescription": "Number of write ops transmitted by the P0 port",
47 "BriefDescription": "Number of read ops transmitted by the P0 port",
54 "BriefDescription": "Number of read ops transmitted by the P0 port which size is 64 bytes",
61 "BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes",
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1232-revA.dts56 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
57 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
58 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
59 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;

12345678910>>...12