Home
last modified time | relevance | path

Searched full:otp (Results 1 – 25 of 213) sorted by relevance

123456789

/linux/drivers/nvmem/
H A Drockchip-otp.c3 * Rockchip OTP Driver
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
85 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
89 ret = reset_control_assert(otp->rst); in rockchip_otp_reset()
91 dev_err(otp->dev, "failed to assert otp phy %d\n", ret); in rockchip_otp_reset()
97 ret = reset_control_deassert(otp->rst); in rockchip_otp_reset()
99 dev_err(otp->dev, "failed to deassert otp phy %d\n", ret); in rockchip_otp_reset()
106 static int rockchip_otp_wait_status(struct rockchip_otp *otp, in rockchip_otp_wait_status() argument
112 ret = readl_poll_timeout_atomic(otp->base + reg, status, in rockchip_otp_wait_status()
[all …]
H A Dlan9662-otpc.c47 static int lan9662_otp_power(struct lan9662_otp *otp, bool up) in lan9662_otp_power() argument
49 void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); in lan9662_otp_power()
53 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_power()
63 static int lan9662_otp_execute(struct lan9662_otp *otp) in lan9662_otp_execute() argument
65 if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), in lan9662_otp_execute()
69 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_execute()
76 static void lan9662_otp_set_address(struct lan9662_otp *otp, u32 offset) in lan9662_otp_set_address() argument
78 writel(0xff & (offset >> 8), OTP_OTP_ADDR_HI(otp->base)); in lan9662_otp_set_address()
79 writel(0xff & offset, OTP_OTP_ADDR_LO(otp->base)); in lan9662_otp_set_address()
82 static int lan9662_otp_read_byte(struct lan9662_otp *otp, u32 offset, u8 *dst) in lan9662_otp_read_byte() argument
[all …]
H A Dsunplus-ocotp.c21 * OTP memory
78 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
94 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
95 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
96 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
97 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
98 otp->base[OTPRX] + OTP_CONTROL_2); in sp_otp_read_real()
99 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) & SEL_BAK_KEY2_MASK & SW_TRIM_EN_MASK in sp_otp_read_real()
101 otp->base[OTPRX] + OTP_CONTROL_2); in sp_otp_read_real()
102 writel((readl(otp->base[OTPRX] + OTP_CONTROL_2) & OTP_RD_PERIOD_MASK) | CPU_CLOCK, in sp_otp_read_real()
[all …]
H A Dmxs-ocotp.c3 * Freescale MXS On-Chip OTP driver
37 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
43 status = readl(otp->base); in mxs_ocotp_wait()
62 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
66 ret = clk_enable(otp->clk); in mxs_ocotp_read()
70 writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()
72 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
77 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET); in mxs_ocotp_read()
82 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
91 *buf++ = readl(otp->base + offset); in mxs_ocotp_read()
[all …]
H A Dnintendo-otp.c3 * Nintendo Wii and Wii U OTP driver
5 * This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
10 * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware/OTP
39 .name = "wii-otp",
44 .name = "wiiu-otp",
68 { .compatible = "nintendo,hollywood-otp", .data = &hollywood_otp_data },
69 { .compatible = "nintendo,latte-otp", .data = &latte_otp_data },
115 .name = "nintendo-otp",
121 MODULE_DESCRIPTION("Nintendo Wii and Wii U OTP driver");
H A Dstm32-romem.c56 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) in stm32_bsec_smc() argument
61 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); in stm32_bsec_smc()
92 u32 otp = i >> 2; in stm32_bsec_read() local
94 if (otp < priv->lower) { in stm32_bsec_read()
99 ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0, in stm32_bsec_read()
102 dev_err(dev, "Can't read data%d (%d)\n", otp, in stm32_bsec_read()
253 * STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
273 * STM32MP25 BSEC OTP: 3 regions of 32-bits data words
274 * lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable
275 * mid OTP (OTP128 to OTP255), bulk (32-bit) programmable
[all …]
H A Dimx-ocotp.c28 * OTP Bank0 Word0
31 * of two consecutive OTP words.
246 * ipg_clk. OTP writes will work at maximum bus frequencies as long in imx_ocotp_set_imx6_timing()
249 * Note: there are minimum timings required to ensure an OTP fuse burns in imx_ocotp_set_imx6_timing()
258 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before in imx_ocotp_set_imx6_timing()
268 * value will mess up a re-load of the shadow registers post OTP in imx_ocotp_set_imx6_timing()
321 /* allow only writing one complete OTP word at a time */ in imx_ocotp_write()
359 * In banked/i.MX7 mode the OTP register bank goes into waddr in imx_ocotp_write()
369 * OTP write/read address specifies one of 128 word address in imx_ocotp_write()
385 * protect programming same OTP bit twice, before program OCOTP will in imx_ocotp_write()
[all …]
H A Dstm32-bsec-optee-ta.c13 * Read OTP memory
15 * [in] value[0].a OTP start offset in byte
18 * [out] memref[1].size Size of OTP to be read
23 * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
28 * Write OTP memory
30 * [in] value[0].a OTP start offset in byte
33 * [in] memref[1].size Size of OTP to be written
38 * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
/linux/Documentation/devicetree/bindings/nvmem/
H A Drockchip,otp.yaml4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3588-otp
29 - const: otp
59 - rockchip,px30-otp
60 - rockchip,rk3308-otp
76 - rockchip,rk3588-otp
85 - const: otp
[all …]
H A Dnintendo-otp.yaml4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
14 See https://wiiubrew.org/wiki/Hardware/OTP
25 - nintendo,hollywood-otp
26 - nintendo,latte-otp
39 otp@d8001ec {
40 compatible = "nintendo,latte-otp";
H A Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
H A Dst,stm32-romem.yaml11 flash, OTP, read-only HW regs... This contains various information such as:
25 - st,stm32f4-otp
40 st,non-secure-otp:
58 compatible = "st,stm32f4-otp";
69 st,non-secure-otp;
H A Dbrcm,ocotp.txt1 Broadcom OTP memory controller
8 - reg: Base address of the OTP controller.
13 otp: otp@301c800 {
H A Dmicrochip,lan9662-otpc.yaml7 title: Microchip LAN9662 OTP Controller (OTPC)
13 OTP controller drives a NVMEM memory where system specific data
40 otpc: otp@e0021000 {
/linux/drivers/mtd/spi-nor/
H A Dotp.c3 * OTP support for SPI NOR flashes
14 #define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len)
15 #define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions)
28 * 256). Thus one "security register" maps to one OTP region.
166 * spi_nor_otp_lock_sr2() - lock the OTP region
168 * @region: OTP region
170 * Lock the OTP region by writing the status register-2. This method is used on
198 * spi_nor_otp_is_locked_sr2() - get the OTP region lock status
200 * @region: OTP region
202 * Retrieve the OTP region lock bit by reading the status register-2. This
[all …]
H A Dcore.h293 * struct spi_nor_otp_organization - Structure to describe the SPI NOR OTP regions
294 * @len: size of one OTP region in bytes.
295 * @base: start address of the OTP area.
296 * @offset: offset between consecutive OTP regions if there are more
298 * @n_regions: number of individual OTP regions.
308 * struct spi_nor_otp_ops - SPI NOR OTP methods
309 * @read: read from the SPI NOR OTP area.
310 * @write: write to the SPI NOR OTP area.
311 * @lock: lock an OTP region.
312 * @erase: erase an OTP region.
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Deeprom.c57 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
58 dev->mt76.otp.size = len; in mt7615_efuse_init()
59 if (!dev->mt76.otp.data) in mt7615_efuse_init()
62 buf = dev->mt76.otp.data; in mt7615_efuse_init()
278 u8 *otp = dev->mt76.otp.data; in mt7615_apply_cal_free_data() local
281 if (!otp) in mt7615_apply_cal_free_data()
285 if (!otp[ical[i]]) in mt7615_apply_cal_free_data()
289 eeprom[ical[i]] = otp[ical[i]]; in mt7615_apply_cal_free_data()
292 eeprom[ical_nocheck[i]] = otp[ical_nocheck[i]]; in mt7615_apply_cal_free_data()
301 u8 *otp = dev->mt76.otp.data; in mt7622_apply_cal_free_data() local
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd.yaml47 "^otp(-[0-9]+)?$":
57 An OTP memory region. Some flashes provide a one-time-programmable
64 - user-otp
65 - factory-otp
95 otp-1 {
96 compatible = "factory-otp";
105 otp-2 {
106 compatible = "user-otp";
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Deeprom.c51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
109 if (!np || !of_property_read_bool(np, "mediatek,eeprom-merge-otp")) in mt7603_apply_cal_free_data()
165 if (dev->mt76.otp.data) { in mt7603_eeprom_init()
167 mt7603_apply_cal_free_data(dev, dev->mt76.otp.data); in mt7603_eeprom_init()
169 memcpy(dev->mt76.eeprom.data, dev->mt76.otp.data, in mt7603_eeprom_init()
/linux/include/linux/mfd/wm831x/
H A Dotp.h3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
73 * R30728 (0x7808) - Factory OTP ID
84 * R30729 (0x7809) - Factory OTP 1
97 * R30730 (0x780A) - Factory OTP 2
104 * R30731 (0x780B) - Factory OTP 3
117 * R30732 (0x780C) - Factory OTP 4
128 * R30733 (0x780D) - Factory OTP 5
135 * R30736 (0x7810) - Customer OTP ID
/linux/drivers/mtd/nand/onenand/
H A DKconfig45 bool "OneNAND OTP Support"
49 Also, 1st Block of NAND Flash Array can be used as OTP.
51 The OTP block can be read, programmed and locked using the same
53 OTP block cannot be erased.
55 OTP block is fully-guaranteed to be a valid block.
/linux/drivers/net/wireless/intel/iwlwifi/dvm/
H A Deeprom.c720 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); in iwl_eeprom_verify_signature()
727 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", in iwl_eeprom_verify_signature()
728 nvm_is_otp ? "OTP" : "EEPROM", gp); in iwl_eeprom_verify_signature()
735 * OTP related functions
751 /* OTP only valid for CP/PP and after */ in iwl_nvm_is_otp()
785 * this is only applicable for HW with OTP shadow RAM in iwl_init_otp_access()
808 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); in iwl_read_otp_word()
816 /* set the uncorrectable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
819 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); in iwl_read_otp_word()
824 /* set the correctable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-agn-hw.h51 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
52 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
53 #define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
54 #define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h47 #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
61 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
67 #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
74 #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
398 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
399 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
400 #define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
401 #define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
548 /** OTP **/
550 /* OTP regions */
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dpalmas-pmic.txt3 The tps659038 for the AM57x class have OTP spins that
5 is not a need to add the OTP spins to the palmas driver. The
35 For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
50 ti,smps-range - OTP has the wrong range set for the hardware so override

123456789