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/linux/drivers/nvmem/
H A Drockchip-otp.c3 * Rockchip OTP Driver
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
85 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
89 ret = reset_control_assert(otp->rst); in rockchip_otp_reset()
91 dev_err(otp->dev, "failed to assert otp phy %d\n", ret); in rockchip_otp_reset()
97 ret = reset_control_deassert(otp->rst); in rockchip_otp_reset()
99 dev_err(otp->dev, "failed to deassert otp phy %d\n", ret); in rockchip_otp_reset()
106 static int rockchip_otp_wait_status(struct rockchip_otp *otp, in rockchip_otp_wait_status() argument
112 ret = readl_poll_timeout_atomic(otp->base + reg, status, in rockchip_otp_wait_status()
[all …]
H A Dlan9662-otpc.c47 static int lan9662_otp_power(struct lan9662_otp *otp, bool up) in lan9662_otp_power() argument
49 void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); in lan9662_otp_power()
53 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_power()
63 static int lan9662_otp_execute(struct lan9662_otp *otp) in lan9662_otp_execute() argument
65 if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), in lan9662_otp_execute()
69 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_execute()
76 static void lan9662_otp_set_address(struct lan9662_otp *otp, u32 offset) in lan9662_otp_set_address() argument
78 writel(0xff & (offset >> 8), OTP_OTP_ADDR_HI(otp->base)); in lan9662_otp_set_address()
79 writel(0xff & offset, OTP_OTP_ADDR_LO(otp->base)); in lan9662_otp_set_address()
82 static int lan9662_otp_read_byte(struct lan9662_otp *otp, u32 offset, u8 *dst) in lan9662_otp_read_byte() argument
[all …]
H A Dsunplus-ocotp.c21 * OTP memory
78 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
94 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
95 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
96 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
97 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
98 otp->base[OTPRX] + OTP_CONTROL_2); in sp_otp_read_real()
99 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) & SEL_BAK_KEY2_MASK & SW_TRIM_EN_MASK in sp_otp_read_real()
101 otp->base[OTPRX] + OTP_CONTROL_2); in sp_otp_read_real()
102 writel((readl(otp->base[OTPRX] + OTP_CONTROL_2) & OTP_RD_PERIOD_MASK) | CPU_CLOCK, in sp_otp_read_real()
[all …]
H A Dmxs-ocotp.c3 * Freescale MXS On-Chip OTP driver
37 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
43 status = readl(otp->base); in mxs_ocotp_wait()
62 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
66 ret = clk_enable(otp->clk); in mxs_ocotp_read()
70 writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()
72 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
77 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET); in mxs_ocotp_read()
82 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
91 *buf++ = readl(otp->base + offset); in mxs_ocotp_read()
[all …]
H A Dnintendo-otp.c3 * Nintendo Wii and Wii U OTP driver
5 * This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
10 * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware/OTP
39 .name = "wii-otp",
44 .name = "wiiu-otp",
68 { .compatible = "nintendo,hollywood-otp", .data = &hollywood_otp_data },
69 { .compatible = "nintendo,latte-otp", .data = &latte_otp_data },
115 .name = "nintendo-otp",
121 MODULE_DESCRIPTION("Nintendo Wii and Wii U OTP driver");
H A Dstm32-romem.c56 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) in stm32_bsec_smc() argument
61 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); in stm32_bsec_smc()
92 u32 otp = i >> 2; in stm32_bsec_read() local
94 if (otp < priv->lower) { in stm32_bsec_read()
99 ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0, in stm32_bsec_read()
102 dev_err(dev, "Can't read data%d (%d)\n", otp, in stm32_bsec_read()
253 * STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
273 * STM32MP25 BSEC OTP: 3 regions of 32-bits data words
274 * lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable
275 * mid OTP (OTP128 to OTP255), bulk (32-bit) programmable
[all …]
H A Dimx-ocotp.c29 * OTP Bank0 Word0
32 * of two consecutive OTP words.
249 * ipg_clk. OTP writes will work at maximum bus frequencies as long in imx_ocotp_set_imx6_timing()
252 * Note: there are minimum timings required to ensure an OTP fuse burns in imx_ocotp_set_imx6_timing()
261 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before in imx_ocotp_set_imx6_timing()
271 * value will mess up a re-load of the shadow registers post OTP in imx_ocotp_set_imx6_timing()
324 /* allow only writing one complete OTP word at a time */ in imx_ocotp_write()
362 * In banked/i.MX7 mode the OTP register bank goes into waddr in imx_ocotp_write()
372 * OTP write/read address specifies one of 128 word address in imx_ocotp_write()
388 * protect programming same OTP bit twice, before program OCOTP will in imx_ocotp_write()
[all …]
H A Dstm32-bsec-optee-ta.c13 * Read OTP memory
15 * [in] value[0].a OTP start offset in byte
18 * [out] memref[1].size Size of OTP to be read
23 * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
28 * Write OTP memory
30 * [in] value[0].a OTP start offset in byte
33 * [in] memref[1].size Size of OTP to be written
38 * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
/linux/Documentation/devicetree/bindings/nvmem/
H A Drockchip,otp.yaml4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3576-otp
18 - rockchip,rk3588-otp
30 - const: otp
60 - rockchip,px30-otp
61 - rockchip,rk3308-otp
79 - rockchip,rk3576-otp
[all …]
H A Dnintendo-otp.yaml4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
14 See https://wiiubrew.org/wiki/Hardware/OTP
25 - nintendo,hollywood-otp
26 - nintendo,latte-otp
39 otp@d8001ec {
40 compatible = "nintendo,latte-otp";
H A Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
H A Dst,stm32-romem.yaml11 flash, OTP, read-only HW regs... This contains various information such as:
25 - st,stm32f4-otp
40 st,non-secure-otp:
58 compatible = "st,stm32f4-otp";
69 st,non-secure-otp;
H A Dbrcm,ocotp.txt1 Broadcom OTP memory controller
8 - reg: Base address of the OTP controller.
13 otp: otp@301c800 {
H A Dmicrochip,lan9662-otpc.yaml7 title: Microchip LAN9662 OTP Controller (OTPC)
13 OTP controller drives a NVMEM memory where system specific data
40 otpc: otp@e0021000 {
H A Dsunplus,sp7021-ocotp.yaml8 title: On-Chip OTP Memory for Sunplus SP7021
58 otp: otp@9c00af00 {
/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd.yaml47 "^otp(-[0-9]+)?$":
57 An OTP memory region. Some flashes provide a one-time-programmable
64 - user-otp
65 - factory-otp
95 otp-1 {
96 compatible = "factory-otp";
105 otp-2 {
106 compatible = "user-otp";
/linux/include/linux/mfd/wm831x/
H A Dotp.h3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
73 * R30728 (0x7808) - Factory OTP ID
84 * R30729 (0x7809) - Factory OTP 1
97 * R30730 (0x780A) - Factory OTP 2
104 * R30731 (0x780B) - Factory OTP 3
117 * R30732 (0x780C) - Factory OTP 4
128 * R30733 (0x780D) - Factory OTP 5
135 * R30736 (0x7810) - Customer OTP ID
/linux/drivers/crypto/
H A Datmel-sha204a.c94 static int atmel_sha204a_otp_read(struct i2c_client *client, u16 addr, u8 *otp) in atmel_sha204a_otp_read() argument
100 dev_err(&client->dev, "failed, invalid otp address %04X\n", in atmel_sha204a_otp_read()
112 memcpy(otp, cmd.data+1, 4); in atmel_sha204a_otp_read()
121 u8 otp[OTP_ZONE_SIZE]; in otp_show() local
127 if (atmel_sha204a_otp_read(client, addr, otp + addr * 4) < 0) { in otp_show()
128 dev_err(dev, "failed to read otp zone\n"); in otp_show()
134 str += sprintf(str, "%02X", otp[i]); in otp_show()
138 static DEVICE_ATTR_RO(otp);
176 /* otp read out */ in atmel_sha204a_probe()
/linux/drivers/mtd/nand/onenand/
H A DKconfig45 bool "OneNAND OTP Support"
49 Also, 1st Block of NAND Flash Array can be used as OTP.
51 The OTP block can be read, programmed and locked using the same
53 OTP block cannot be erased.
55 OTP block is fully-guaranteed to be a valid block.
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dpcie.c359 struct brcmf_otp_params otp; member
1953 brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n", in brcmf_pcie_parse_otp_sys_vendor()
1976 strscpy(devinfo->otp.module, p, len + 1); in brcmf_pcie_parse_otp_sys_vendor()
1979 strscpy(devinfo->otp.vendor, p, len + 1); in brcmf_pcie_parse_otp_sys_vendor()
1982 strscpy(devinfo->otp.version, p, len + 1); in brcmf_pcie_parse_otp_sys_vendor()
1990 brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n", in brcmf_pcie_parse_otp_sys_vendor()
1991 devinfo->otp.module, devinfo->otp.vendor, in brcmf_pcie_parse_otp_sys_vendor()
1992 devinfo->otp.version); in brcmf_pcie_parse_otp_sys_vendor()
1994 if (!devinfo->otp.module[0] || in brcmf_pcie_parse_otp_sys_vendor()
1995 !devinfo->otp.vendor[0] || in brcmf_pcie_parse_otp_sys_vendor()
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-agn-hw.h51 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
52 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
53 #define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
54 #define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h47 #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
61 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
67 #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
74 #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
398 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
399 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
400 #define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
401 #define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
548 /** OTP **/
550 /* OTP regions */
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dpalmas-pmic.txt3 The tps659038 for the AM57x class have OTP spins that
5 is not a need to add the OTP spins to the palmas driver. The
35 For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
50 ti,smps-range - OTP has the wrong range set for the hardware so override
/linux/include/uapi/mtd/
H A Dmtd-abi.h170 /* OTP mode selection */
227 /* Set OTP (One-Time Programmable) mode (factory vs. user) */
229 /* Get number of OTP (One-Time Programmable) regions */
231 /* Get all OTP (One-Time Programmable) info about MTD */
315 * @MTD_FILE_MODE_NORMAL: OTP disabled, ECC enabled
316 * @MTD_FILE_MODE_OTP_FACTORY: OTP enabled in factory mode
317 * @MTD_FILE_MODE_OTP_USER: OTP enabled in user mode
318 * @MTD_FILE_MODE_RAW: OTP disabled, ECC disabled
/linux/drivers/mtd/nand/raw/
H A Dnand_macronix.c82 /* RANDEN and RANDOPT OTP bits are programmed */ in macronix_nand_randomizer_check_enable()
113 rand_otp = of_property_read_bool(dn, "mxic,enable-randomizer-otp"); in macronix_nand_onfi_init()
336 /* Always report that OTP is unlocked. Reason is that this in macronix_30lfxg18ac_get_otp_info()
337 * type of flash chip doesn't provide way to check that OTP in macronix_30lfxg18ac_get_otp_info()
339 * volatile register. Technically OTP region could be locked in macronix_30lfxg18ac_get_otp_info()
342 * always returns -EOPNOTSUPP) and thus we report that OTP in macronix_30lfxg18ac_get_otp_info()
421 dev_err(&mtd->dev, "failed to perform OTP IO: %i\n", ret); in __macronix_30lfxg18ac_rw_otp()
425 dev_err(&mtd->dev, "failed to leave OTP mode after %s\n", in __macronix_30lfxg18ac_rw_otp()

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