xref: /freebsd/sys/contrib/device-tree/Bindings/display/ti/ti,am65x-dss.yaml (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 Texas Instruments Incorporated
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Texas Instruments AM65x Display Subsystem
9
10maintainers:
11  - Jyri Sarha <jsarha@ti.com>
12  - Tomi Valkeinen <tomi.valkeinen@ti.com>
13
14description: |
15  The AM625 and AM65x TI Keystone Display SubSystem has two output
16  ports and two video planes. In AM65x DSS, the first video port
17  supports 1 OLDI TX and in AM625 DSS, the first video port output is
18  internally routed to 2 OLDI TXes. The second video port supports DPI
19  format. The first plane is full video plane with all features and the
20  second is a "lite plane" without scaling support.
21  The AM62L display subsystem has a single output port which supports DPI
22  format but it only supports single video "lite plane" which does not support
23  scaling. The output port is routed to SoC boundary via DPI interface and same
24  DPI signals are also routed internally to DSI Tx controller present within the
25  SoC. Due to clocking limitations only one of the interface i.e. either DSI or
26  DPI can be used at once.
27
28properties:
29  compatible:
30    enum:
31      - ti,am625-dss
32      - ti,am62a7-dss
33      - ti,am62l-dss
34      - ti,am65x-dss
35
36  reg:
37    description:
38      Addresses to each DSS memory region described in the SoC's TRM.
39    items:
40      - description: common DSS register area
41      - description: VIDL1 light video plane
42      - description: VID video plane
43      - description: OVR1 overlay manager for vp1
44      - description: OVR2 overlay manager for vp2
45      - description: VP1 video port 1
46      - description: VP2 video port 2
47      - description: common1 DSS register area
48
49  reg-names:
50    items:
51      - const: common
52      - const: vidl1
53      - const: vid
54      - const: ovr1
55      - const: ovr2
56      - const: vp1
57      - const: vp2
58      - const: common1
59
60  clocks:
61    items:
62      - description: fck DSS functional clock
63      - description: vp1 Video Port 1 pixel clock
64      - description: vp2 Video Port 2 pixel clock
65
66  clock-names:
67    items:
68      - const: fck
69      - const: vp1
70      - const: vp2
71
72  assigned-clocks:
73    minItems: 1
74    maxItems: 3
75
76  assigned-clock-parents:
77    minItems: 1
78    maxItems: 3
79
80  interrupts:
81    maxItems: 1
82
83  power-domains:
84    maxItems: 1
85    description: phandle to the associated power domain
86
87  dma-coherent:
88    type: boolean
89
90  ports:
91    $ref: /schemas/graph.yaml#/properties/ports
92
93    properties:
94      port@0:
95        $ref: /schemas/graph.yaml#/properties/port
96        description:
97          For AM65x DSS, the OLDI output port node from video port 1.
98          For AM625 DSS, the internal DPI output port node from video
99          port 1.
100          For AM62A7 DSS, the port is tied off inside the SoC.
101          For AM62L DSS, the DSS DPI output port node from video port 1
102          or DSI Tx controller node connected to video port 1.
103        properties:
104          endpoint@0:
105            $ref: /schemas/graph.yaml#/properties/endpoint
106            description:
107              For AM625 DSS, VP Connection to OLDI0.
108              For AM65X DSS, OLDI output from the SoC.
109
110          endpoint@1:
111            $ref: /schemas/graph.yaml#/properties/endpoint
112            description:
113              For AM625 DSS, VP Connection to OLDI1.
114
115        anyOf:
116          - required:
117              - endpoint
118          - required:
119              - endpoint@0
120              - endpoint@1
121
122      port@1:
123        $ref: /schemas/graph.yaml#/properties/port
124        description:
125          The DSS DPI output port node from video port 2
126
127  ti,am65x-oldi-io-ctrl:
128    $ref: /schemas/types.yaml#/definitions/phandle
129    description:
130      phandle to syscon device node mapping OLDI IO_CTRL registers.
131      The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
132      following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
133      and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
134      interface to work.
135
136  max-memory-bandwidth:
137    $ref: /schemas/types.yaml#/definitions/uint32
138    description:
139      Input memory (from main memory to dispc) bandwidth limit in
140      bytes per second
141
142  oldi-transmitters:
143    description:
144      Child node under the DSS, to describe all the OLDI transmitters connected
145      to the DSS videoports.
146    type: object
147    additionalProperties: false
148
149    properties:
150      "#address-cells":
151        const: 1
152
153      "#size-cells":
154        const: 0
155
156    patternProperties:
157      '^oldi@[0-1]$':
158        $ref: ti,am625-oldi.yaml#
159        description: OLDI transmitters connected to the DSS VPs
160
161allOf:
162  - if:
163      properties:
164        compatible:
165          contains:
166            const: ti,am62a7-dss
167    then:
168      properties:
169        oldi-transmitters: false
170        ports:
171          properties:
172            port@0: false
173  - if:
174      properties:
175        compatible:
176          contains:
177            const: ti,am62l-dss
178    then:
179      properties:
180        ports:
181          properties:
182            port@1: false
183
184  - if:
185      properties:
186        compatible:
187          contains:
188            enum:
189              - ti,am62l-dss
190              - ti,am65x-dss
191    then:
192      properties:
193        oldi-transmitters: false
194        ports:
195          properties:
196            port@0:
197              properties:
198                endpoint@1: false
199
200required:
201  - compatible
202  - reg
203  - reg-names
204  - clocks
205  - clock-names
206  - interrupts
207  - ports
208
209additionalProperties: false
210
211examples:
212  - |
213    #include <dt-bindings/interrupt-controller/arm-gic.h>
214    #include <dt-bindings/interrupt-controller/irq.h>
215    #include <dt-bindings/soc/ti,sci_pm_domain.h>
216
217    dss: dss@4a00000 {
218        compatible = "ti,am65x-dss";
219        reg = <0x04a00000 0x1000>, /* common */
220              <0x04a02000 0x1000>, /* vidl1 */
221              <0x04a06000 0x1000>, /* vid */
222              <0x04a07000 0x1000>, /* ovr1 */
223              <0x04a08000 0x1000>, /* ovr2 */
224              <0x04a0a000 0x1000>, /* vp1 */
225              <0x04a0b000 0x1000>, /* vp2 */
226              <0x04a01000 0x1000>; /* common1 */
227        reg-names = "common", "vidl1", "vid",
228                "ovr1", "ovr2", "vp1", "vp2", "common1";
229        ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
230        power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
231        clocks =        <&k3_clks 67 1>,
232                        <&k3_clks 216 1>,
233                        <&k3_clks 67 2>;
234        clock-names = "fck", "vp1", "vp2";
235        interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
236        ports {
237            #address-cells = <1>;
238            #size-cells = <0>;
239            port@0 {
240                reg = <0>;
241                oldi_out0: endpoint {
242                    remote-endpoint = <&lcd_in0>;
243                };
244            };
245        };
246    };
247
248  - |
249    #include <dt-bindings/interrupt-controller/arm-gic.h>
250    #include <dt-bindings/interrupt-controller/irq.h>
251    #include <dt-bindings/soc/ti,sci_pm_domain.h>
252
253    bus {
254        #address-cells = <2>;
255        #size-cells = <2>;
256        dss1: dss@30200000 {
257            compatible = "ti,am625-dss";
258            reg = <0x00 0x30200000 0x00 0x1000>, /* common */
259                  <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
260                  <0x00 0x30206000 0x00 0x1000>, /* vid */
261                  <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
262                  <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
263                  <0x00 0x3020a000 0x00 0x1000>, /* vp1 */
264                  <0x00 0x3020b000 0x00 0x1000>, /* vp2 */
265                  <0x00 0x30201000 0x00 0x1000>; /* common1 */
266            reg-names = "common", "vidl1", "vid",
267                        "ovr1", "ovr2", "vp1", "vp2", "common1";
268            power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
269            clocks =        <&k3_clks 186 6>,
270                            <&vp1_clock>,
271                            <&k3_clks 186 2>;
272            clock-names = "fck", "vp1", "vp2";
273            interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
274            oldi-transmitters {
275                #address-cells = <1>;
276                #size-cells = <0>;
277                oldi0: oldi@0 {
278                    reg = <0>;
279                    clocks = <&k3_clks 186 0>;
280                    clock-names = "serial";
281                    ti,companion-oldi = <&oldi1>;
282                    ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
283                    ports {
284                        #address-cells = <1>;
285                        #size-cells = <0>;
286                        port@0 {
287                            reg = <0>;
288                            oldi0_in: endpoint {
289                                remote-endpoint = <&dpi0_out0>;
290                            };
291                        };
292                        port@1 {
293                            reg = <1>;
294                            oldi0_out: endpoint {
295                                remote-endpoint = <&panel_in0>;
296                            };
297                        };
298                    };
299                };
300                oldi1: oldi@1 {
301                    reg = <1>;
302                    clocks = <&k3_clks 186 0>;
303                    clock-names = "serial";
304                    ti,secondary-oldi;
305                    ti,companion-oldi = <&oldi0>;
306                    ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
307                    ports {
308                        #address-cells = <1>;
309                        #size-cells = <0>;
310                        port@0 {
311                            reg = <0>;
312                            oldi1_in: endpoint {
313                                remote-endpoint = <&dpi0_out1>;
314                            };
315                        };
316                        port@1 {
317                            reg = <1>;
318                            oldi1_out: endpoint {
319                                remote-endpoint = <&panel_in1>;
320                            };
321                        };
322                    };
323                };
324            };
325            ports {
326                #address-cells = <1>;
327                #size-cells = <0>;
328                port@0 {
329                    #address-cells = <1>;
330                    #size-cells = <0>;
331                    reg = <0>;
332                    dpi0_out0: endpoint@0 {
333                        reg = <0>;
334                        remote-endpoint = <&oldi0_in>;
335                    };
336                    dpi0_out1: endpoint@1 {
337                        reg = <1>;
338                        remote-endpoint = <&oldi1_in>;
339                    };
340                };
341                port@1 {
342                    reg = <1>;
343                    dpi1_out: endpoint {
344                        remote-endpoint = <&hdmi_bridge>;
345                    };
346                };
347            };
348        };
349    };
350