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/linux/Documentation/devicetree/bindings/arm/
H A Dsecure.txt1 * ARM Secure world bindings
4 "Normal" and "Secure". Most devicetree consumers (including the Linux
6 world or the Secure world. However some devicetree consumers are
8 visible only in the Secure address space, only in the Normal address
10 virtual machine which boots Secure firmware and wants to tell the
13 The general principle of the naming scheme for Secure world bindings
14 is that any property that needs a different value in the Secure world
15 can be supported by prefixing the property name with "secure-". So for
16 instance "secure-foo" would override "foo". For property names with
17 a vendor prefix, the Secure variant of "vendor,foo" would be
[all …]
/linux/Documentation/devicetree/bindings/nvmem/
H A Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
20 - $ref: nvmem-deprecated-cells.yaml#
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H A Dqcom,sec-qfprom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/qcom,sec-qfprom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc, Secure QFPROM Efuse
10 - Komal Bajaj <quic_kbajaj@quicinc.com>
14 protected from non-secure access. In such situations, the OS have to use
15 secure calls to read the region.
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
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/linux/arch/arm/common/
H A Dsecure_cntvoff.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Initialization of CNTVOFF register from secure mode
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
16 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
17 * then it should be handled by the secure code. The CPU must implement
21 mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Dmmu.json9 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1",
12 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1"
15 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1",
18 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1"
H A Dexception.json12 …ructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1",
15 …tructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1"
/linux/drivers/tee/optee/
H A Doptee_smc.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2021, Linaro Limited
8 #include <linux/arm-smccc.h>
28 * Normal cached memory (write-back), shareable for SMP systems and not
36 * 32-bit registers.
44 * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b.
75 * Used by non-secure world to figure out which Trusted OS is installed.
78 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
88 * Used by non-secure world to figure out which version of the Trusted OS
92 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
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H A Doptee_rpc_cmd.h1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2016-2021, Linaro Limited
14 * RPC communication with tee-supplicant is reversed compared to normal
23 * 1970-01-01 00:00:00 +0000 (UTC).
31 * Notification from/to secure world.
33 * If secure world needs to wait for something, for instance a mutex, it
34 * does a notification wait request instead of spinning in secure world.
35 * Conversely can a synchronous notification can be sent when a secure
39 * which instead is sent via a non-secure interrupt.
71 /* Memory that can be shared with a non-secure user space application */
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H A Doptee_msg.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2021, Linaro Limited
12 * This file defines the OP-TEE message protocol (ABI) used to communicate
13 * with an instance of OP-TEE running in secure world.
21 * Part 1 - formatting of messages
41 * Meta parameter to be absorbed by the Secure OS and not passed
49 * Pointer to a list of pages used to register user-defined SHM buffer.
52 * list of page addresses. OP-TEE core can reconstruct contiguous buffer from
64 * uint64_t pages_array[OPTEE_MSG_NONCONTIG_PAGE_SIZE/sizeof(uint64_t) - 1];
98 * Page size used in non-contiguous buffer entries
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/linux/arch/arm/mach-omap2/
H A Domap-secure.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP Secure API infrastructure.
11 #include <linux/arm-smccc.h>
23 #include "omap-secure.h"
39 * We only check that the OP-TEE node is present and available. The in omap_optee_init_check()
40 * OP-TEE kernel driver is not needed for the type of interaction made in omap_optee_init_check()
41 * with OP-TEE here so the driver's status is not checked. in omap_optee_init_check()
50 * omap_secure_dispatcher - Routine to dispatch low power secure
55 * @arg1, arg2, arg3 args4: Parameters passed to secure API
57 * Return the non-zero error value on failure.
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H A Domap-headsmp.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
58 .arch armv7-a
110 * CortexA9 r1pX and r2pX. The Control Register secure
112 * bit 0 == Secure Enable
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
H A Domap-smp.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
116 * by ROM code in "secure world" using the smc call and there is no
150 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA in omap4_secondary_init()
151 * init and for CPU1, a secure PPA API provided. CPU0 must be ON in omap4_secondary_init()
153 * OMAP443X GP devices- SMP bit isn't accessible. in omap4_secondary_init()
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/linux/Documentation/tee/
H A Dop-tee.rst1 .. SPDX-License-Identifier: GPL-2.0
4 OP-TEE (Open Portable Trusted Execution Environment)
7 The OP-TEE driver handles OP-TEE [1] based TEEs. Currently it is only the ARM
8 TrustZone based OP-TEE solution that is supported.
10 Lowest level of communication with OP-TEE builds on ARM SMC Calling
11 Convention (SMCCC) [2], which is the foundation for OP-TEE's SMC interface
12 [3] used internally by the driver. Stacked on top of that is OP-TEE Message
15 OP-TEE SMC interface provides the basic functions required by SMCCC and some
16 additional functions specific for OP-TEE. The most interesting functions are:
18 - OPTEE_SMC_FUNCID_CALLS_UID (part of SMCCC) returns the version information
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/linux/drivers/soc/tegra/cbb/
H A Dtegra-cbb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
16 #include <soc/tegra/tegra-cbb.h>
42 rd_str = (cache & BIT(2)) ? "Read-Allocate " : ""; in tegra_cbb_print_cache()
43 wr_str = (cache & BIT(3)) ? "Write-Allocate" : ""; in tegra_cbb_print_cache()
46 buff_str = "Device Non-Bufferable"; in tegra_cbb_print_cache()
48 tegra_cbb_print_err(file, "\t Cache\t\t\t: 0x%x -- %s%s%s%s\n", in tegra_cbb_print_cache()
57 secure_str = (prot & 0x2) ? "Non-Secure" : "Secure"; in tegra_cbb_print_prot()
60 tegra_cbb_print_err(file, "\t Protection\t\t: 0x%x -- %s, %s, %s Access\n", in tegra_cbb_print_prot()
66 struct tegra_cbb *cbb = file->private; in tegra_cbb_err_show()
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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra194-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
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/linux/arch/arm64/boot/dts/tesla/
H A Dfsd.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
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/linux/Documentation/devicetree/bindings/arm/samsung/
H A Dsamsung-secure-firmware.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Secure Firmware
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - const: samsung,secure-firmware
19 Address of non-secure SYSRAM used for communication with firmware.
23 - compatible
24 - reg
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/linux/drivers/net/wireless/silabs/wfx/
H A Dhif_rx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Handling of the chip-to-host events (aka indications) of the hardware API.
5 * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
6 * Copyright (c) 2010, ST-Ericsson
24 int cmd = hif->id; in wfx_hif_generic_confirm()
25 int len = le16_to_cpu(hif->len) - 4; /* drop header */ in wfx_hif_generic_confirm()
27 WARN(!mutex_is_locked(&wdev->hif_cmd.lock), "data locking error"); in wfx_hif_generic_confirm()
29 if (!wdev->hif_cmd.buf_send) { in wfx_hif_generic_confirm()
30 dev_warn(wdev->dev, "unexpected confirmation: 0x%.2x\n", cmd); in wfx_hif_generic_confirm()
31 return -EINVAL; in wfx_hif_generic_confirm()
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/linux/drivers/vfio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "VFIO Non-Privileged userspace driver framework"
11 VFIO provides a framework for secure userspace device drivers.
12 See Documentation/driver-api/vfio.rst for more details.
25 to set up secure DMA context for device access. This interface does
64 bool "VFIO No-IOMMU support"
69 considered secure. VFIO No-IOMMU mode enables IOMMU groups for
70 devices without IOMMU backing for the purpose of re-using the VFIO
71 infrastructure in a non-secure mode. Use of this mode will result
89 cause the VFIO code create a top-level debug/vfio directory
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/linux/Documentation/devicetree/bindings/mailbox/
H A Darm,mhu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
19 be a 'Secure' resource, hence can't be used by Linux running NS.
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
38 - arm,mhu-doorbell
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/linux/Documentation/devicetree/bindings/misc/
H A Dqcom,fastrpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 The FastRPC implements an IPC (Inter-Processor Communication)
25 - adsp
26 - mdsp
27 - sdsp
28 - cdsp
29 - cdsp1
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/linux/drivers/firmware/efi/libstub/
H A Dsecureboot.c1 // SPDX-License-Identifier: GPL-2.0
3 * Secure boot handling.
26 * Determine whether we're in secure boot mode.
38 efi_err("Could not determine UEFI Secure Boot status.\n"); in efi_get_secureboot()
46 * variable doesn't have the non-volatile attribute set, we might as in efi_get_secureboot()
53 /* If it fails, we don't care why. Default to secure */ in efi_get_secureboot()
60 efi_info("UEFI Secure Boot is enabled.\n"); in efi_get_secureboot()
/linux/drivers/watchdog/
H A Dkeembay_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Intel Keem Bay non-secure watchdog.
8 #include <linux/arm-smccc.h>
20 /* Non-secure watchdog register offsets */
61 return readl(wdt->base + offset); in keembay_wdt_readl()
66 writel(WDT_UNLOCK, wdt->base + TIM_SAFE); in keembay_wdt_writel()
67 writel(val, wdt->base + offset); in keembay_wdt_writel()
74 keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate); in keembay_wdt_set_timeout_reg()
82 if (wdog->pretimeout) in keembay_wdt_set_pretimeout_reg()
83 th_val = wdog->timeout - wdog->pretimeout; in keembay_wdt_set_pretimeout_reg()
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/linux/Documentation/devicetree/bindings/bus/
H A Dst,stm32mp25-rifsc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gatien Chevallier <gatien.chevallier@foss.st.com>
19 - RISC registers associated with RISUP logic (resource isolation device unit
20 for peripherals), assign all non-RIF aware peripherals to zero, one or
21 any security domains (secure, privilege, compartment).
22 - RIMC registers: associated with RIMU logic (resource isolation master
23 unit), assign all non RIF-aware bus master to one security domain by
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/linux/Documentation/devicetree/bindings/firmware/
H A Dbrcm,kona-smc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/firmware/brcm,kona-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family Secure Monitor bounce buffer
10 A bounce buffer used for non-secure to secure communications.
13 - Florian Fainelli <f.fainelli@gmail.com>
18 - enum:
19 - brcm,bcm11351-smc
20 - brcm,bcm21664-smc
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