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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-pcf857x.txt1 * PCF857x-compatible I/O expanders
3 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
4 driven high by a pull-up current source or driven low to ground. This combines
14 - compatible: should be one of the following.
15 - "maxim,max7328": For the Maxim MAX7378
16 - "maxim,max7329": For the Maxim MAX7329
17 - "nxp,pca8574": For the NXP PCA8574
18 - "nxp,pca8575": For the NXP PCA8575
19 - "nxp,pca9670": For the NXP PCA9670
20 - "nxp,pca9671": For the NXP PCA9671
[all …]
H A Dnxp,pcf8575.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nxp,pcf8575.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCF857x-compatible I/O expanders
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
14 driven high by a pull-up current source or driven low to ground. This
25 - maxim,max7328
26 - maxim,max7329
[all …]
/freebsd/sys/modules/dtb/imx6/
H A DMakefile3 nxp/imx/imx6dl-cubox-i.dts \
4 nxp/imx/imx6q-cubox-i.dts \
5 nxp/imx/imx6dl-hummingboard.dts \
6 nxp/imx/imx6q-hummingboard.dts \
7 nxp/imx/imx6dl-nitrogen6x.dts \
8 nxp/imx/imx6q-nitrogen6_max.dts \
9 nxp/imx/imx6q-nitrogen6x.dts \
10 nxp/imx/imx6qp-nitrogen6_max.dts \
11 nxp/imx/imx6sx-nitrogen6sx.dts \
12 nxp/imx/imx6dl-riotboard.dts \
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dnxp,imx8-jpeg.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX8QXP/QM JPEG decoder/encoder
10 - Mirela Rabulea <mirela.rabulea@nxp.com>
12 description: |-
14 ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
20 - items:
22 - nxp,imx8qxp-jpgdec
[all …]
H A Damphion,vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
16 on NXP i.MX8Q SoCs.
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
25 - nxp,imx8qm-vpu
[all …]
H A Dnxp,imx8mq-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Hantro G1/G2 video decode accelerators present on i.MX8MQ SoCs.
19 - const: nxp,imx8mq-vpu
21 - const: nxp,imx8mq-vpu-g1
22 - const: nxp,imx8mq-vpu-g2
[all …]
H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,dw100.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP DW100 Dewarper core
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
24 - nxp,imx8mp-dw100
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnxp,imx95-blk-ctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nxp,imx95-blk-ctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX95 Block Control
10 - Peng Fan <peng.fan@nxp.com>
15 - enum:
16 - nxp,imx95-lvds-csr
17 - nxp,imx95-display-csr
18 - nxp,imx95-camera-csr
[all …]
H A Dnxp,imx95-display-master-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX95 Display Master Block Control
10 - Peng Fan <peng.fan@nxp.com>
15 - const: nxp,imx95-display-master-csr
16 - const: syscon
21 power-domains:
27 '#clock-cells':
[all …]
H A Dimx8mm-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Mini Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Mini clock control module is an integrated clock controller, which
18 const: fsl,imx8mm-ccm
25 - description: 32k osc
26 - description: 24m osc
[all …]
H A Dimx8mn-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8mn-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Nano Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Nano clock control module is an integrated clock controller, which
18 const: fsl,imx8mn-ccm
25 - description: 32k osc
26 - description: 24m osc
[all …]
H A Dimx8mp-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8mp-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Plus Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Plus clock control module is an integrated clock controller, which
18 const: fsl,imx8mp-ccm
25 - description: 32k osc
26 - description: 24m osc
[all …]
H A Dfsl,imx8m-anatop.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,imx8m-anatop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Family Anatop Module
10 - Peng Fan <peng.fan@nxp.com>
13 NXP i.MX8M Family anatop PLL module which generates PLL to CCM root.
18 - enum:
19 - fsl,imx8mm-anatop
20 - fsl,imx8mq-anatop
[all …]
H A Dimx8mq-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Quad Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Quad clock control module is an integrated clock controller, which
18 const: fsl,imx8mq-ccm
25 - description: 32k osc
26 - description: 25m osc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dleds-pca9532.txt1 *NXP - pca9532 PWM LED Driver
3 The PCA9532 family is SMBus I/O expander optimized for dimming LEDs.
7 - compatible:
8 "nxp,pca9530"
9 "nxp,pca9531"
10 "nxp,pca9532"
11 "nxp,pca9533"
12 - reg - I2C slave address
14 Each led is represented as a sub-node of the nxp,pca9530.
16 Optional sub-node properties:
[all …]
H A Dnxp,pca953x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/nxp,pca953
[all...]
H A Dleds-pca955x.txt1 * NXP - pca955x LED driver
4 to control LEDs can be used as general purpose I/Os. The GPIO pins can
5 be input or output, and output pins can also be pulse-width controlled.
8 - compatible : should be one of :
9 "nxp,pca9550"
10 "nxp,pca9551"
11 "nxp,pca9552"
13 "nxp,pca9553"
14 - #address-cells: must be 1
15 - #size-cells: must be 0
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dnxp,dwmac-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8/9 DWMAC glue layer
10 - Clark Wang <xiaoning.wang@nxp.com>
11 - Shawn Guo <shawnguo@kernel.org>
12 - NXP Linux Team <linux-imx@nxp.com>
20 - nxp,imx8mp-dwmac-eqos
21 - nxp,imx8dxl-dwmac-eqos
[all …]
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-facebook-catalina.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/usb/pd.h>
8 #include <dt-bindings/leds/leds-pca955x.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/i2c/i2c.h>
14 compatible = "facebook,catalina-bmc", "aspeed,ast2600";
64 stdout-path = "serial4:57600n8";
[all …]
H A Daspeed-bmc-delta-ahe50dc.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g4.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
9 compatible = "regulator-output"; \
10 vout-supply = <&efuse##n>; \
19 shunt-resistor-micro-ohms = <675>; \
22 regulator-name = __stringify(efuse##num##-reg); \
28 model = "Delta Power AHE-50DC";
29 compatible = "delta,ahe50dc-bmc", "aspeed,ast2400";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/nxp,sja1000.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Memory mapped SJA1000 CAN controller from NXP (formerly Philips)
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A Dimx8m-soc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/imx8m-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Series SoC
10 - Alice Guo <alice.guo@nxp.com>
13 NXP i.MX8M series SoCs contain fuse entries from which SoC Unique ID can be
21 - fsl,imx8mm
22 - fsl,imx8mn
23 - fsl,imx8mp
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dnxp,imx95-scmi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2024 NXP
4 ---
5 $id: http://devicetree.org/schemas/firmware/nxp,imx95-scmi-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: i.MX System Control and Management Interface (SCMI) Pinctrl Protocol
11 - Peng Fan <peng.fan@nxp.com>
14 - $ref: /schemas/pinctrl/pinctrl.yaml
31 be found in <arch/arm64/boot/dts/freescale/imx95-pinfunc.h>. The last
32 integer CONFIG is the pad setting value like pull-up on this pin.
[all …]
H A Dnxp,imx95-scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2024 NXP
4 ---
5 $id: http://devicetree.org/schemas/firmware/nxp,imx95-scmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: i.MX95 System Control and Management Interface(SCMI) Vendor Protocols Extension
11 - Peng Fan <peng.fan@nxp.com>
15 $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node'
23 $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node'
30 nxp,ctrl-ids:
[all …]

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