Searched full:mx95 (Results 1 – 11 of 11) sorted by relevance
7 title: NXP i.MX95 Display Master Block Control
33 Please refer to i.MX95 Reference Manual for detailed CONFIG settings.
124 Build the clock driver for i.MX95 BLK CTL
555 MODULE_DESCRIPTION("NXP i.MX95 blk ctl driver");
18 and i.MX95.
14 model = "TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2";
16 model = "PHYTEC Libra i.MX95 RDK FPSC";
10 model = "PHYTEC phyCORE-i.MX95 FPSC";
260 * Regarding the Signal Descriptions of i.MX95 PCIe PHY, ref_use_pad is in imx95_pcie_select_ref_clk_src()903 * From i.MX95 PCIe PHY perspective, the COLD reset toggle in imx95_pcie_core_reset()912 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe. in imx95_pcie_core_reset()1219 * (i.MX95) │ │ │ in imx_pcie_add_lut_by_rid()
245 /* TODO: currently, i.MX95 ENETC driver does not support advanced features */ in enetc_pf_netdev_setup()
352 * Some SoCs (e.g. i.MX95, i.MX8QM, i.MX8DXL) support up to 200MHz.