xref: /freebsd/sys/contrib/device-tree/Bindings/media/amphion,vpu.yaml (revision 2846c90520eb4cc74e24d586a0ea0f4a0006bc73) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Amphion VPU codec IP
8
9maintainers:
10  - Ming Qian <ming.qian@nxp.com>
11  - Shijie Qin <shijie.qin@nxp.com>
12
13description: |-
14  The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
15  on NXP i.MX8Q SoCs.
16
17properties:
18  $nodename:
19    pattern: "^vpu@[0-9a-f]+$"
20
21  compatible:
22    items:
23      - enum:
24          - nxp,imx8qm-vpu
25          - nxp,imx8qxp-vpu
26
27  reg:
28    maxItems: 1
29
30  power-domains:
31    maxItems: 1
32
33  "#address-cells":
34    const: 1
35
36  "#size-cells":
37    const: 1
38
39  ranges: true
40
41patternProperties:
42  "^mailbox@[0-9a-f]+$":
43    description:
44      Each vpu encoder or decoder correspond a MU, which used for communication
45      between driver and firmware. Implement via mailbox on driver.
46    $ref: /schemas/mailbox/fsl,mu.yaml#
47
48
49  "^vpu-core@[0-9a-f]+$":
50    description:
51      Each core correspond a decoder or encoder, need to configure them
52      separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
53      has one decoder and one encoder.
54    type: object
55
56    properties:
57      compatible:
58        items:
59          - enum:
60              - nxp,imx8q-vpu-decoder
61              - nxp,imx8q-vpu-encoder
62
63      reg:
64        maxItems: 1
65
66      power-domains:
67        maxItems: 1
68
69      mbox-names:
70        items:
71          - const: tx0
72          - const: tx1
73          - const: rx
74
75      mboxes:
76        description:
77          List of phandle of 2 MU channels for tx, 1 MU channel for rx.
78        maxItems: 3
79
80      memory-region:
81        description:
82          Phandle to the reserved memory nodes to be associated with the
83          remoteproc device. The reserved memory nodes should be carveout nodes,
84          and should be defined as per the bindings in
85          Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
86        items:
87          - description: region reserved for firmware image sections.
88          - description: region used for RPC shared memory between firmware and
89                         driver.
90
91    required:
92      - compatible
93      - reg
94      - power-domains
95      - mbox-names
96      - mboxes
97      - memory-region
98
99    additionalProperties: false
100
101required:
102  - compatible
103  - reg
104  - power-domains
105
106additionalProperties: false
107
108examples:
109  # Device node example for i.MX8QM platform:
110  - |
111    #include <dt-bindings/firmware/imx/rsrc.h>
112
113    vpu: vpu@2c000000 {
114      compatible = "nxp,imx8qm-vpu";
115      ranges = <0x2c000000 0x2c000000 0x2000000>;
116      reg = <0x2c000000 0x1000000>;
117      #address-cells = <1>;
118      #size-cells = <1>;
119      power-domains = <&pd IMX_SC_R_VPU>;
120
121      mu_m0: mailbox@2d000000 {
122        compatible = "fsl,imx6sx-mu";
123        reg = <0x2d000000 0x20000>;
124        interrupts = <0 472 4>;
125        #mbox-cells = <2>;
126        power-domains = <&pd IMX_SC_R_VPU_MU_0>;
127      };
128
129      mu1_m0: mailbox@2d020000 {
130        compatible = "fsl,imx6sx-mu";
131        reg = <0x2d020000 0x20000>;
132        interrupts = <0 473 4>;
133        #mbox-cells = <2>;
134        power-domains = <&pd IMX_SC_R_VPU_MU_1>;
135      };
136
137      mu2_m0: mailbox@2d040000 {
138        compatible = "fsl,imx6sx-mu";
139        reg = <0x2d040000 0x20000>;
140        interrupts = <0 474 4>;
141        #mbox-cells = <2>;
142        power-domains = <&pd IMX_SC_R_VPU_MU_2>;
143      };
144
145      vpu_core0: vpu-core@2d080000 {
146        compatible = "nxp,imx8q-vpu-decoder";
147        reg = <0x2d080000 0x10000>;
148        power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
149        mbox-names = "tx0", "tx1", "rx";
150        mboxes = <&mu_m0 0 0>,
151                 <&mu_m0 0 1>,
152                 <&mu_m0 1 0>;
153        memory-region = <&decoder_boot>, <&decoder_rpc>;
154      };
155
156      vpu_core1: vpu-core@2d090000 {
157        compatible = "nxp,imx8q-vpu-encoder";
158        reg = <0x2d090000 0x10000>;
159        power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
160        mbox-names = "tx0", "tx1", "rx";
161        mboxes = <&mu1_m0 0 0>,
162                 <&mu1_m0 0 1>,
163                 <&mu1_m0 1 0>;
164        memory-region = <&encoder1_boot>, <&encoder1_rpc>;
165      };
166
167      vpu_core2: vpu-core@2d0a0000 {
168        reg = <0x2d0a0000 0x10000>;
169        compatible = "nxp,imx8q-vpu-encoder";
170        power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
171        mbox-names = "tx0", "tx1", "rx";
172        mboxes = <&mu2_m0 0 0>,
173                 <&mu2_m0 0 1>,
174                 <&mu2_m0 1 0>;
175        memory-region = <&encoder2_boot>, <&encoder2_rpc>;
176      };
177    };
178
179...
180