Searched full:mx7 (Results 1 – 17 of 17) sorted by relevance
18 is found in the i.MX6UL/L, i.MX7 and i.MX8M[MQ] SoCs.32 tristate "NXP MIPI CSI-2 CSIS receiver found on i.MX7 and i.MX8 models"40 v3.3/v3.6.3 found on some i.MX7 and i.MX8 SoCs.
201 bool "i.MX7 Dual support"206 This enables support for Freescale i.MX7 Dual processor.214 This enables support for Freescale i.MX7 Ultra Low Power processor.
15 DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
82 DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
7 title: Freescale i.MX7 Dual Clock Controller15 for the full list of i.MX7 Dual clock IDs.
7 title: Freescale i.MX7 System Reset Controller19 <dt-bindings/reset/imx7-reset.h> for i.MX7,
3 i.MX7 Video Capture Driver9 The i.MX7 contrary to the i.MX5/6 family does not contain an Image Processing13 For image capture the i.MX7 has three units:30 For additional information, please refer to the latest versions of the i.MX7
10 model = "Freescale i.MX7 SabreSD RevA Board";
10 model = "Freescale i.MX7 SabreSD Board";
362 * In banked/i.MX7 mode the OTP register bank goes into waddr in imx_ocotp_write()402 * Note: on i.MX7 there are four data fields to write for banked write in imx_ocotp_write()408 /* Banked/i.MX7 mode */ in imx_ocotp_write()643 MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
156 MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 and i.MX7 Secure Non-Volatile Stora…
7 title: i.MX7 and i.MX8 CSI bridge (CMOS Sensor Interface)
114 tristate "i.MX7/8 Reset Driver"120 This enables the reset controller driver for i.MX7 SoCs.
5 * i.MX7 System Reset Controller (SRC) driver406 MODULE_DESCRIPTION("NXP i.MX7 reset driver");
113 This adds cpufreq driver support for Freescale i.MX7/i.MX8M
56 /* i.MX7 specific */
179 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */