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/linux/drivers/media/platform/nxp/
H A DKconfig18 is found in the i.MX6UL/L, i.MX7 and i.MX8M[MQ] SoCs.
32 tristate "NXP MIPI CSI-2 CSIS receiver found on i.MX7 and i.MX8 models"
40 v3.3/v3.6.3 found on some i.MX7 and i.MX8 SoCs.
/linux/arch/arm/mach-imx/
H A DKconfig201 bool "i.MX7 Dual support"
206 This enables support for Freescale i.MX7 Dual processor.
214 This enables support for Freescale i.MX7 Ultra Low Power processor.
H A Dmach-imx7d-cm4.c15 DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
H A Dmach-imx7d.c82 DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
/linux/Documentation/devicetree/bindings/clock/
H A Dimx7d-clock.yaml7 title: Freescale i.MX7 Dual Clock Controller
15 for the full list of i.MX7 Dual clock IDs.
/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx-mipi-csi2.yaml7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
16 compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
H A Dnxp,imx7-csi.yaml7 title: i.MX7 and i.MX8 CSI bridge (CMOS Sensor Interface)
/linux/Documentation/devicetree/bindings/reset/
H A Dfsl,imx7-src.yaml7 title: Freescale i.MX7 System Reset Controller
19 <dt-bindings/reset/imx7-reset.h> for i.MX7,
/linux/Documentation/admin-guide/media/
H A Dimx7.rst3 i.MX7 Video Capture Driver
9 The i.MX7 contrary to the i.MX5/6 family does not contain an Image Processing
13 For image capture the i.MX7 has three units:
30 For additional information, please refer to the latest versions of the i.MX7
/linux/drivers/nvmem/
H A Dimx-ocotp.c359 * In banked/i.MX7 mode the OTP register bank goes into waddr in imx_ocotp_write()
399 * Note: on i.MX7 there are four data fields to write for banked write in imx_ocotp_write()
405 /* Banked/i.MX7 mode */ in imx_ocotp_write()
640 MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
H A Dsnvs_lpgpr.c156 MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 and i.MX7 Secure Non-Volatile Stora…
H A DKconfig334 i.MX6 and i.MX7 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d-sdb-reva.dts10 model = "Freescale i.MX7 SabreSD RevA Board";
H A Dimx7s-warp.dts13 model = "Element14 Warp i.MX7 Board";
H A Dimx7d-nitrogen7.dts11 model = "Boundary Devices i.MX7 Nitrogen7 Board";
H A Dimx7d-sdb.dts10 model = "Freescale i.MX7 SabreSD Board";
/linux/drivers/reset/
H A DKconfig107 tristate "i.MX7/8 Reset Driver"
113 This enables the reset controller driver for i.MX7 SoCs.
H A Dreset-imx7.c5 * i.MX7 System Reset Controller (SRC) driver
406 MODULE_DESCRIPTION("NXP i.MX7 reset driver");
/linux/drivers/cpufreq/
H A DKconfig.arm114 This adds cpufreq driver support for Freescale i.MX7/i.MX8M
/linux/Documentation/devicetree/bindings/arm/
H A Dfsl.yaml860 - element14,imx7s-warp # Element14 Warp i.MX7 Board
885 - fsl,imx7d-sdb # i.MX7 SabreSD Board
886 - fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
889 - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
908 Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
/linux/drivers/pci/controller/dwc/
H A Dpci-imx6.c179 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */