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/linux/arch/arm/mach-imx/
H A Dmach-imx6q.c173 * SoCs that identify as i.MX6Q >= rev 2.0 are really i.MX6QP. in imx6q_init_machine()
174 * Quirk: i.MX6QP revision = i.MX6Q revision - (1, 0), in imx6q_init_machine()
175 * e.g. i.MX6QP rev 1.1 identifies as i.MX6Q rev 2.1. in imx6q_init_machine()
179 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", in imx6q_init_machine()
H A Dhardware.h79 * mx6q:
/linux/Documentation/admin-guide/media/
H A Dimx.rst108 The following shows the media topologies for the i.MX6Q SabreSD and
109 i.MX6Q SabreAuto. Refer to these diagrams in the entity descriptions
123 :alt: Diagram of the i.MX6Q SabreSD media pipeline topology
126 Media pipeline graph on i.MX6Q SabreSD
129 :alt: Diagram of the i.MX6Q SabreAuto media pipeline topology
132 Media pipeline graph on i.MX6Q SabreAuto
409 i.MX6Q SabreLite with OV5642 and OV5640
463 i.MX6Q SabreAuto with ADV7180 decoder
466 On the i.MX6Q SabreAuto, an on-board ADV7180 SD decoder is connected to the
579 i.MX6Q SabreSD with MIPI CSI-2 OV5640
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/linux/Documentation/devicetree/bindings/thermal/
H A Dimx-thermal.yaml27 The interrupt output of the controller, i.MX6Q has IRQ_HIGH which
29 i.MX6SX and i.MX7S/D have two more IRQs than i.MX6Q, one is IRQ_LOW
/linux/Documentation/usb/
H A Dchipidea.rst9 with 2 Freescale i.MX6Q sabre SD boards.
35 1) Power up 2 Freescale i.MX6Q sabre SD boards with gadget class driver loaded
/linux/Documentation/devicetree/bindings/media/
H A Dfsl-vdoa.txt4 The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose
/linux/drivers/clocksource/
H A Dtimer-imx-gpt.c24 * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
25 * - MX6DL, MX6SX, MX6Q(rev1.1+)
484 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S in imx31_timer_init_dt()
/linux/Documentation/devicetree/bindings/nvmem/
H A Dimx-ocotp.yaml16 i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL,
/linux/drivers/soc/imx/
H A Dsoc-imx.c99 soc_id = "i.MX6Q"; in imx_soc_device_init()
/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.h16 #define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */
H A Dgpmi-nand.c832 * is 16000ps, but in mx6q, we use 12000ps.
934 * during the change of the divide factor on i.MX6Q/UL/SX. On i.MX7/8, in gpmi_nfc_apply_timings()
/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,imx-weim.yaml63 WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx35-pinctrl.yaml130 i.MX6DL/i.MX6Q/i.MX6SL specific bits
/linux/drivers/gpu/drm/imx/ipuv3/
H A Dimx-ldb.c533 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel in imx_ldb_probe()
/linux/drivers/clk/imx/
H A Dclk-imx6q.c465 /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ in imx6q_clocks_init()
910 * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it in imx6q_clocks_init()
/linux/drivers/ata/
H A Dahci_imx.c961 * TIMER1MS register on i.MX53, i.MX6Q and i.MX6QP only. in imx_ahci_probe()
/linux/drivers/tty/serial/
H A Dimx.c179 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
1181 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.c2208 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others. in dw_hdmi_clear_overflow()
/linux/drivers/net/ethernet/freescale/
H A Dfec_main.c2571 * Reference Manual has an error on this, and gets fixed on i.MX6Q in fec_enet_mii_init()