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/linux/Documentation/devicetree/bindings/mailbox/
H A Dfsl,mu.yaml4 $id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
7 title: NXP i.MX Messaging Unit (MU)
15 and control) through the MU interface. The MU also provides the ability
18 Because the MU manages the messaging between processors, the MU uses
20 Therefore, the MU must synchronize the accesses from one side to the
21 other. The MU accomplishes synchronization using two sets of matching
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
29 - const: fsl,imx8ulp-mu
30 - const: fsl,imx8-mu-scu
[all …]
/linux/Documentation/devicetree/bindings/firmware/
H A Dfsl,scu.yaml17 The AP communicates with the SC using a multi-ported MU module found
18 in the LSIO subsystem. The current definition of this MU module provides
20 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
21 with the LSIO DSC IP bus. The SC firmware will communicate with this MU
50 A list of phandles of TX MU channels followed by a list of phandles of
51 RX MU channels. The list may include at the end one more optional MU
53 channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"
54 compatible, 4 TX and 4 RX channels otherwise. All MU channels must be
55 within the same MU instance. Cross instances are not allowed. The MU
61 - description: TX0 MU channel
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qxp-ss-lsio.dtsi65 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
69 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
73 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
77 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
81 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
85 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
89 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
93 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
H A Dimx8qm-ss-lsio.dtsi78 compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
82 compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
86 compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
90 compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
94 compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
98 compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
102 compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
106 compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
H A Dimx8dxl-ss-lsio.dtsi93 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
98 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
103 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
108 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
113 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
118 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
H A Dimx8-ss-vpu.dtsi16 compatible = "fsl,imx6sx-mu";
25 compatible = "fsl,imx6sx-mu";
34 compatible = "fsl,imx6sx-mu";
H A Dimx8ulp-evk.dts90 mboxes = <&mu 0 1>,
91 <&mu 1 1>,
92 <&mu 3 1>;
233 &mu {
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,mu-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
15 and control) through the MU interface. The MU also provides the ability
19 Because the MU manages the messaging between processors, the MU uses
21 Therefore, the MU must synchronize the accesses from one side to the
22 other. The MU accomplishes synchronization using two sets of matching
25 MU can work as msi interrupt controller to do doorbell
33 - fsl,imx6sx-mu-msi
34 - fsl,imx7ulp-mu-msi
35 - fsl,imx8ulp-mu-msi
[all …]
/linux/kernel/bpf/
H A Dtnum.c64 u64 sm, sv, sigma, chi, mu; in tnum_add() local
70 mu = chi | a.mask | b.mask; in tnum_add()
71 return TNUM(sv & ~mu, mu); in tnum_add()
76 u64 dv, alpha, beta, chi, mu; in tnum_sub() local
82 mu = chi | a.mask | b.mask; in tnum_sub()
83 return TNUM(dv & ~mu, mu); in tnum_sub()
98 u64 v, mu; in tnum_or() local
101 mu = a.mask | b.mask; in tnum_or()
102 return TNUM(v, mu & ~v); in tnum_or()
107 u64 v, mu; in tnum_xor() local
[all …]
/linux/drivers/scsi/
H A Dhptiop.c142 static u64 mv_outbound_read(struct hpt_iopmu_mv __iomem *mu) in mv_outbound_read() argument
144 u32 outbound_tail = readl(&mu->outbound_tail); in mv_outbound_read()
145 u32 outbound_head = readl(&mu->outbound_head); in mv_outbound_read()
150 memcpy_fromio(&p, &mu->outbound_q[mu->outbound_tail], 8); in mv_outbound_read()
155 writel(outbound_tail, &mu->outbound_tail); in mv_outbound_read()
163 u32 inbound_head = readl(&hba->u.mv.mu->inbound_head); in mv_inbound_write()
169 memcpy_toio(&hba->u.mv.mu->inbound_q[inbound_head], &p, 8); in mv_inbound_write()
170 writel(head, &hba->u.mv.mu->inbound_head); in mv_inbound_write()
213 msg = readl(&hba->u.mv.mu->outbound_msg); in iop_intr_mv()
222 while ((tag = mv_outbound_read(hba->u.mv.mu))) in iop_intr_mv()
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Damphion,vpu.yaml45 Each vpu encoder or decoder correspond a MU, which used for communication
47 $ref: /schemas/mailbox/fsl,mu.yaml#
78 List of phandle of 2 MU channels for tx, 1 MU channel for rx.
123 compatible = "fsl,imx6sx-mu";
131 compatible = "fsl,imx6sx-mu";
139 compatible = "fsl,imx6sx-mu";
/linux/drivers/irqchip/
H A Dirq-imx-mu-msi.c3 * Freescale MU used as MSI controller
137 .name = "MU",
219 .prefix = "MU-MSI-",
243 /* Register offset of different version MU IP */
357 dev_err(dev, "Failed to add device_link to mu a.\n"); in imx_mu_of_init()
368 dev_err(dev, "Failed to add device_link to mu a.\n"); in imx_mu_of_init()
437 IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init)
438 IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init)
439 IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init)
444 MODULE_DESCRIPTION("Freescale MU MSI controller driver");
/linux/drivers/firmware/arm_scmi/
H A Doptee.c
/linux/drivers/mtd/nand/raw/atmel/
H A Dpmecc.c176 s32 *mu; member
361 /* Reserve space for mu, dmu and delta. */ in atmel_pmecc_create_user()
375 user->mu = (s32 *)PTR_ALIGN(user->smu + in atmel_pmecc_create_user()
379 user->dmu = user->mu + req->ecc.strength + 1; in atmel_pmecc_create_user()
491 s32 *mu = user->mu; in atmel_pmecc_get_sigma() local
513 /* Mu */ in atmel_pmecc_get_sigma()
514 mu[0] = -1; in atmel_pmecc_get_sigma()
523 delta[0] = (mu[0] * 2 - lmu[0]) >> 1; in atmel_pmecc_get_sigma()
527 /* Mu */ in atmel_pmecc_get_sigma()
528 mu[1] = 0; in atmel_pmecc_get_sigma()
[all …]
/linux/drivers/input/
H A Dinput-mt.c358 static int adjust_dual(int *begin, int step, int *end, int eq, int mu) in adjust_dual() argument
379 if (c == 0 || (c > mu && (!eq || mu > 0))) in adjust_dual()
382 if (s < 0 && mu <= 0) in adjust_dual()
391 static void find_reduced_matrix(int *w, int nr, int nc, int nrc, int mu) in find_reduced_matrix() argument
397 adjust_dual(w + i, nr, w + i + nrc, nr <= nc, mu); in find_reduced_matrix()
400 sum += adjust_dual(w + i, 1, w + i + nr, nc <= nr, mu); in find_reduced_matrix()
408 int mu) in input_mt_set_matrix() argument
422 *w++ = dx * dx + dy * dy - mu; in input_mt_set_matrix()
488 int mu = 2 * dmax * dmax; in input_mt_assign_slots() local
498 nrc = input_mt_set_matrix(mt, pos, num_pos, mu); in input_mt_assign_slots()
[all …]
/linux/drivers/net/wireless/ath/ath11k/
H A Ddebugfs_htt_stats.h536 /* MU MIMO stats per hwQ */
657 u32 delayed_bar_1; /* MU user 1 */
658 u32 delayed_bar_2; /* MU user 2 */
659 u32 delayed_bar_3; /* MU user 3 */
660 u32 delayed_bar_4; /* MU user 4 */
661 u32 delayed_bar_5; /* MU user 5 */
662 u32 delayed_bar_6; /* MU user 6 */
663 u32 delayed_bar_7; /* MU user 7 */
672 u32 ac_mu_mimo_brpoll_1; /* MU user 1 */
673 u32 ac_mu_mimo_brpoll_2; /* MU user 2 */
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Dbf.c67 rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n"); in rtw_bf_assoc()
242 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n"); in rtw_bf_enable_bfee_mu()
323 rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n"); in rtw_bf_set_gid_table()
355 /* MU Retry Limit */ in rtw_bf_phy_init()
358 /* Disable Tx MU-MIMO until sounding done */ in rtw_bf_phy_init()
360 /* Clear validity of MU STAs */ in rtw_bf_phy_init()
364 /* MU-MIMO Option as default value */ in rtw_bf_phy_init()
369 /* MU-MIMO Control as default value */ in rtw_bf_phy_init()
371 /* Set MU NDPA rate & BW source */ in rtw_bf_phy_init()
/linux/net/mac80211/
H A Ddebugfs_sta.c640 PFLAG(MU_BEAMFORMER_CAPABLE, "MU-BEAMFORMER-CAPABLE"); in link_sta_vht_capa_read()
641 PFLAG(MU_BEAMFORMEE_CAPABLE, "MU-BEAMFORMEE-CAPABLE"); in link_sta_vht_capa_read()
768 PFLAG(MAC, 2, MU_CASCADING, "MU-CASCADING"); in link_sta_he_capa_read()
806 PFLAG(MAC, 5, OM_CTRL_UL_MU_DATA_DIS_RX, "OM-CTRL-UL-MU-DATA-DIS-RX"); in link_sta_he_capa_read()
858 PFLAG(PHY, 2, UL_MU_FULL_MU_MIMO, "UL-MU-FULL-MU-MIMO"); in link_sta_he_capa_read()
859 PFLAG(PHY, 2, UL_MU_PARTIAL_MU_MIMO, "UL-MU-PARTIAL-MU-MIMO"); in link_sta_he_capa_read()
897 "RX-PARTIAL-BW-SU-IN-20MHZ-MU"); in link_sta_he_capa_read()
901 PFLAG(PHY, 4, MU_BEAMFORMER, "MU-BEAMFORMER"); in link_sta_he_capa_read()
913 PFLAG(PHY, 5, NG16_MU_FEEDBACK, "NG16-MU-FEEDBACK"); in link_sta_he_capa_read()
916 PFLAG(PHY, 6, CODEBOOK_SIZE_75_MU, "CODEBOOK-SIZE-75-MU"); in link_sta_he_capa_read()
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dfsl,imx-rproc.yaml50 (see mailbox/fsl,mu.yaml)
144 mboxes = <&mu 0 1
145 &mu 1 1
146 &mu 3 1>;
/linux/drivers/mailbox/
H A Dimx-mailbox.c139 /* MU reset */
586 /* IPC MU should be with IRQF_NO_SUSPEND set */ in imx_mu_startup()
794 /* Set default MU configuration */ in imx_mu_init_generic()
828 /* Set default MU configuration */ in imx_mu_init_specific()
911 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); in imx_mu_probe()
915 dev_err(dev, "Failed to init MU\n"); in imx_mu_probe()
1041 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
1042 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
1043 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
1044 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dmac.h400 * Per each trigger-based AC, (set by MU EDCA Parameter set info-element)
402 * The MU-TIMER is reloaded w/ MU_TIME each time a frame from the AC is sent via
408 * allowed till the MU-TIMER is 0
409 * @mu_time: MU time in 8TU units
509 * @STA_CTXT_HE_MU_EDCA_CW: indicates that there is an element of MU EDCA
544 * @IWL_HE_HTC_UL_MU_RESP_SCHED: HE UL MU response schedule
591 * @trig_based_txf: MU EDCA Parameter set for the trigger based traffic queues
625 /* The below fields are set via MU EDCA parameter set element */
651 * @trig_based_txf: MU EDCA Parameter set for the trigger based traffic queues
693 /* The below fields are set via MU EDCA parameter set element */
[all …]
H A Drx.h343 /* info type: HE MU/MU-EXT */
358 /* TSF overload high dword For EHT-MU/TB rates*/
360 /* info type: EHT-MU */
376 /* info type: HE MU-EXT */
392 /* info type: HE MU-EXT */
401 /* info type: HE MU-EXT */
413 /* info type: EHT-MU-EXT */
425 /* info type: EHT-MU-EXT */
432 /* info type: EHT-MU-EXT */
446 /* info type: EHT-MU */
/linux/sound/usb/
H A Dmixer_maps.c41 USB_IN[1] --->FU[2]------------------------------+->MU[16]-->PU[17]-+->FU[18]--+->EU[27]--+->EU[21]…
43 USB_IN[3] -+->SU[5]-->FU[6]--+->MU[14] ->PU[15]->+ | | | …
70 /* 14: MU (w/o controls) */
72 /* 16: MU (w/o controls) */
123 /* 15: MU */
135 Dig_IN[4]---+->FU[6]-->MU[16]->FU[18]-+->EU[21]->SU[31]----->FU[30]->Hph_OUT[20]
154 /* 16: MU w/o controls */
225 /* 6: MU */
230 /* 11: MU */
253 /* 0xb: MU (w/o controls) */
[all …]
/linux/arch/riscv/crypto/
H A Daes-riscv64-zvkned-zvkb.S79 vsetivli zero, 4, e32, m1, ta, mu
91 vsetvli VL_E32, LEN32, e32, m4, ta, mu
98 vsetvli VL_E32, LEN32, e32, m4, ta, mu
128 vsetivli zero, 4, e32, m1, ta, mu
/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Ddebugfs.c256 "VHT SU", "VHT 2MU", "VHT 3MU", "VHT 4MU" in mt7915_muru_stats_show()
259 "HE SU", "HE EXT", "HE 2MU", "HE 3MU", "HE 4MU", in mt7915_muru_stats_show()
264 "HE 2MU", "HE 3MU", "HE 4MU", "HE SU", "HE 2RU", in mt7915_muru_stats_show()
295 seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); in mt7915_muru_stats_show()
310 seq_printf(file, "\nTotal non-HE MU-MIMO DL PPDU count: %lld", in mt7915_muru_stats_show()
332 seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); in mt7915_muru_stats_show()
361 seq_printf(file, "\nTotal HE MU-MIMO DL PPDU count: %lld", in mt7915_muru_stats_show()
381 seq_puts(file, "\nTrigger-based Uplink MU-MIMO\nData Type: "); in mt7915_muru_stats_show()
412 seq_printf(file, "\nTotal HE MU-MIMO UL TB PPDU count: %lld", in mt7915_muru_stats_show()
747 /* Tx SU & MU counters */ in mt7915_txbf_stat_read_phy()

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