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/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,mtu2.yaml4 $id: http://devicetree.org/schemas/timer/renesas,mtu2.yaml#
7 title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)
14 The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs
18 independent. The MTU2 hardware supports five channels indexed from 0 to 4.
24 - renesas,mtu2-r7s72100 # RZ/A1H
25 - const: renesas,mtu2
68 mtu2: timer@fcff0000 {
69 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
H A Drenesas,rz-mtu3.yaml18 for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
35 - [MTU1, MTU2]
38 of MTU1 and MTU2 (when TMDR3.LWA = 1)
56 - [MTU0/MTU5, MTU1, MTU2, and MTU8]
57 - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
76 MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
77 counting mode in which MTU1 and MTU2 are cascaded.
84 count1 - MTU2 16-bit phase counting
85 count2 - MTU1+ MTU2 32-bit phase counting
98 pwm3 - MTU2.MTIOC2A PWM mode 1
[all …]
/linux/Documentation/devicetree/bindings/soc/renesas/
H A Drenesas-soc.yaml45 …(g)?ether(avb)?|gpio|hscif|(r)?i[i2]c|imr|intc|ipmmu|irqc|jpu|mmcif|msiof|mtu2|pci(e)?|pfc|pwm|[rq…
53 - renesas,mtu2-r7s72100
/linux/drivers/clocksource/
H A Dsh_mtu2.c3 * SuperH Timer Support - MTU2
488 { "sh-mtu2", 0 },
494 { .compatible = "renesas,mtu2" },
527 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
/linux/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7264.c97 [MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
126 CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),
H A Dclock-sh7269.c133 [MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */
160 CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),
H A Dsetup-sh7201.c366 .name = "sh-mtu2",
413 /* enable MTU2 clock */ in plat_early_device_setup()
H A Dsetup-sh7203.c285 .name = "sh-mtu2",
350 /* enable MTU2 clock */ in plat_early_device_setup()
H A Dsetup-mxg.c123 .name = "sh-mtu2",
H A Dsetup-sh7206.c286 /* enable MTU2 clock */ in plat_early_device_setup()
H A Dsetup-sh7269.c467 .name = "sh-mtu2",
H A Dsetup-sh7264.c445 .name = "sh-mtu2",
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7734.c336 MTU2, enumerator
428 INTC_VECT(MTU2, 0xE20),
473 MTU2,
523 { MTU2, RGPVG, MIMLB, IEBUS } },
/linux/drivers/counter/
H A Drz-mtu3-cnt.c39 * LWA: MTU1/MTU2 Combination Longword Access Control
436 * 32-bit phase counting need MTU1 and MTU2 to create 32-bit in rz_mtu3_initialize_counter()
713 RZ_MTU3_PHASE_SIGNAL(SIGNAL_C_ID, "MTU2 MTCLKC"),
714 RZ_MTU3_PHASE_SIGNAL(SIGNAL_D_ID, "MTU2 MTCLKD"),
/linux/arch/sh/kernel/cpu/
H A Dclock-cpg.c64 clk_add_alias("fck", "sh-mtu2", "peripheral_clk", NULL); in cpg_clk_init()
/linux/arch/arm64/boot/dts/renesas/
H A Drzg2ul-smarc-pinfunction.dtsi54 mtu2-pwm {
/linux/arch/arm/boot/dts/renesas/
H A Dr7s72100-gr-peach.dts97 &mtu2 {
/linux/drivers/pwm/
H A Dpwm-rz-mtu3.c85 * and MTU2 channel is 1 compared to 2 on others.