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Searched full:mtu1 (Results 1 – 5 of 5) sorted by relevance

/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,rz-mtu3.yaml18 for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
35 - [MTU1, MTU2]
38 of MTU1 and MTU2 (when TMDR3.LWA = 1)
56 - [MTU0/MTU5, MTU1, MTU2, and MTU8]
57 - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
76 MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
77 counting mode in which MTU1 and MTU2 are cascaded.
83 count0 - MTU1 16-bit phase counting
85 count2 - MTU1+ MTU2 32-bit phase counting
97 pwm2 - MTU1.MTIOC1A PWM mode 1
[all …]
/linux/drivers/counter/
H A Drz-mtu3-cnt.c39 * LWA: MTU1/MTU2 Combination Longword Access Control
436 * 32-bit phase counting need MTU1 and MTU2 to create 32-bit in rz_mtu3_initialize_counter()
711 RZ_MTU3_PHASE_SIGNAL(SIGNAL_A_ID, "MTU1 MTCLKA"),
712 RZ_MTU3_PHASE_SIGNAL(SIGNAL_B_ID, "MTU1 MTCLKB"),
/linux/include/linux/mfd/
H A Drz-mtu3.h91 #define RZ_MTU3_TMDR3 0x191 /* MTU1 Timer Mode Register 3 */
/linux/drivers/pwm/
H A Dpwm-rz-mtu3.c84 * The MTU channels are {0..4, 6, 7} and the number of IO on MTU1
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi44 mtu1: mtu@101e3000 { label