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39 * LWA: MTU1/MTU2 Combination Longword Access Control436 * 32-bit phase counting need MTU1 and MTU2 to create 32-bit in rz_mtu3_initialize_counter()711 RZ_MTU3_PHASE_SIGNAL(SIGNAL_A_ID, "MTU1 MTCLKA"),712 RZ_MTU3_PHASE_SIGNAL(SIGNAL_B_ID, "MTU1 MTCLKB"),
91 #define RZ_MTU3_TMDR3 0x191 /* MTU1 Timer Mode Register 3 */
84 * The MTU channels are {0..4, 6, 7} and the number of IO on MTU1
44 mtu1: mtu@101e3000 { label