Searched +full:mtu1 +full:- +full:mtu2 (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)10 - Biju Das <biju.das.jz@bp.renesas.com>13 This hardware block consists of eight 16-bit timer channels and one14 32-bit timer channel. It supports the following specifications:15 - Pulse input/output: 28 lines max16 - Pulse input 3 lines[all …]
1 // SPDX-License-Identifier: GPL-2.010 #include <linux/mfd/rz-mtu3.h>39 * LWA: MTU1/MTU2 Combination Longword Access Control40 * 0: 16-bit, 1: 32-bit66 * struct rz_mtu3_cnt - MTU3 counter private data72 * @mtu_16bit_max: Cache for 16-bit counters73 * @mtu_32bit_max: Cache for 32-bit counters102 return &priv->ch[ch_id]; in rz_mtu3_get_ch()110 pm_runtime_get_sync(priv->ch->dev); in rz_mtu3_is_counter_invalid()111 tmdr = rz_mtu3_shared_reg_read(priv->ch, RZ_MTU3_TMDR3); in rz_mtu3_is_counter_invalid()[all …]
1 // SPDX-License-Identifier: GPL-2.08 …* https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?lang…11 * - When PWM is disabled, the output is driven to Hi-Z.12 * - While the hardware supports both polarities, the driver (for now)14 * - HW uses one counter and two match components to configure duty_cycle16 * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM18 * - MTU{1, 2} channels have a single IO, whereas all other HW channels have20 * - Each IO is modelled as an independent PWM channel.21 * - rz_mtu3_channel_io_map table is used to map the PWM channel to the29 #include <linux/mfd/rz-mtu3.h>[all …]