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/freebsd/sys/x86/cpufreq/
H A Dhwpstate_amd.c80 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) (((msr) >> 4) & 0x7)
81 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7) argument
83 #define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F) argument
84 #define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07)
85 #define AMD_10H_11H_CUR_FID(msr) ((msr) argument
78 AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) global() argument
79 AMD_10H_11H_GET_PSTATE_LIMIT(msr) global() argument
82 AMD_10H_11H_CUR_DID(msr) global() argument
86 AMD_17H_CUR_IDD(msr) global() argument
87 AMD_17H_CUR_VID(msr) global() argument
88 AMD_17H_CUR_DID(msr) global() argument
89 AMD_17H_CUR_FID(msr) global() argument
174 uint64_t msr; hwpstate_goto_pstate() local
266 uint64_t msr; hwpstate_get() local
352 uint64_t msr; hwpstate_probe() local
430 uint64_t msr; hwpstate_get_info_from_msr() local
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H A Dp4tcc.c164 * status MSR until we've set it ourselves. in p4tcc_attach()
261 uint64_t mask, msr; in p4tcc_set() local
282 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_set()
284 msr &= ~(mask | TCC_ENABLE_ONDEMAND); in p4tcc_set()
286 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; in p4tcc_set()
287 wrmsr(MSR_THERM_CONTROL, msr); in p4tcc_set()
296 if (msr & TCC_ENABLE_ONDEMAND) in p4tcc_set()
308 uint64_t msr; in p4tcc_get() local
324 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_get()
325 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); in p4tcc_get()
/freebsd/usr.sbin/bhyve/
H A Duart_emul.c91 uint8_t msr; /* Modem status register (R/W) */
108 uint8_t msr; in modem_status()
113 * reflected back into MSR. in modem_status()
115 msr = 0; in modem_status()
117 msr |= MSR_CTS; in modem_status()
119 msr |= MSR_DSR; in modem_status()
121 msr |= MSR_RI; in modem_status()
123 msr |= MSR_DCD; in modem_status()
129 msr = MSR_DCD | MSR_DSR; in modem_status()
131 assert((msr in modem_status()
92 uint8_t msr; /* Modem status register (R/W) */ global() member
109 uint8_t msr; modem_status() local
221 uint8_t msr; uart_ns16550_write() local
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/freebsd/sys/amd64/amd64/
H A Dinitcpu.c67 uint64_t msr; in init_amd() local
95 * Hypervisors do not provide access to the errata MSR, in init_amd()
97 * MSR write shall be done on host and persist globally in init_amd()
116 msr = rdmsr(MSR_NB_CFG1); in init_amd()
117 msr |= (uint64_t)1 << 54; in init_amd()
118 wrmsr(MSR_NB_CFG1, msr); in init_amd()
125 * The relevant MSR bit is not documented in the BKDG, in init_amd()
130 msr = rdmsr(0xc001102a); in init_amd()
131 msr &= ~((uint64_t)1 << 24); in init_amd()
132 wrmsr(0xc001102a, msr); in init_amd()
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/freebsd/usr.sbin/cpucontrol/
H A Dcpucontrol.837 .Fl m Ar msr
43 .Fl m Ar msr Ns = Ns Ar value
49 .Fl m Ar msr Ns &= Ns Ar mask
55 .Fl m Ar msr Ns |= Ns Ar mask
102 .It Fl m Ar msr
103 Show value of the specified MSR.
106 .It Fl m Ar msr Ns = Ns Ar value
109 in the specified MSR register.
114 .It Fl m Ar msr Ns &= Ns Ar mask
117 and the current MSR value in the MSR register.
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/freebsd/sys/dev/coretemp/
H A Dcoretemp.c30 * Device driver for Intel's On Die thermal sensor via MSR.
157 uint64_t msr; in coretemp_attach() local
172 * is queried via a MSR, so we stop here. in coretemp_attach()
190 msr = rdmsr(MSR_BIOS_SIGN); in coretemp_attach()
191 msr = msr >> 32; in coretemp_attach()
192 if (msr < 0x39) { in coretemp_attach()
207 * On some Core 2 CPUs, there's an undocumented MSR that in coretemp_attach()
213 msr = rdmsr(MSR_IA32_EXT_CONFIG); in coretemp_attach()
214 if (msr & (1 << 30)) in coretemp_attach()
235 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. in coretemp_attach()
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/freebsd/sys/powerpc/powerpc/
H A Dfpu.c49 register_t msr; in save_fpu_int() local
57 msr = mfmsr(); in save_fpu_int()
59 mtmsr(msr | PSL_FP | PSL_VSX); in save_fpu_int()
61 mtmsr(msr | PSL_FP); in save_fpu_int()
97 mtmsr(msr); in save_fpu_int()
103 register_t msr; in enable_fpu() local
137 msr = mfmsr(); in enable_fpu()
139 mtmsr(msr | PSL_FP | PSL_VSX); in enable_fpu()
141 mtmsr(msr | PSL_FP); in enable_fpu()
178 mtmsr(msr); in enable_fpu()
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H A Daltivec.c48 int msr; in save_vec_int() local
56 msr = mfmsr(); in save_vec_int()
57 mtmsr(msr | PSL_VEC); in save_vec_int()
80 mtmsr(msr); in save_vec_int()
87 int msr; in enable_vec() local
118 msr = mfmsr(); in enable_vec()
119 mtmsr(msr | PSL_VEC); in enable_vec()
142 mtmsr(msr); in enable_vec()
183 register_t msr; in disable_vec() local
191 msr = mfmsr() & ~PSL_VEC; in disable_vec()
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/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A Dmemory.json22 …c pair of event select and counter MSR, and with specific event codes and predefine mask bit value…
34 …c pair of event select and counter MSR, and with specific event codes and predefine mask bit value…
46 …c pair of event select and counter MSR, and with specific event codes and predefine mask bit value…
58 …c pair of event select and counter MSR, and with specific event codes and predefine mask bit value…
70 …c pair of event select and counter MSR, and with specific event codes and predefine mask bit value…
82 …c pair of event select and counter MSR, and with specific event codes and predefine mask bit value…
/freebsd/sys/amd64/vmm/
H A Dvmm_lapic.c131 x2apic_msr(u_int msr) in x2apic_msr() argument
133 return (msr >= 0x800 && msr <= 0xBFF); in x2apic_msr()
137 x2apic_msr_to_regoff(u_int msr) in x2apic_msr_to_regoff() argument
140 return ((msr - 0x800) << 4); in x2apic_msr_to_regoff()
144 lapic_msr(u_int msr) in lapic_msr() argument
147 return (x2apic_msr(msr) || msr == MSR_APICBASE); in lapic_msr()
151 lapic_rdmsr(struct vcpu *vcpu, u_int msr, uint64_t *rval, bool *retu) in lapic_rdmsr() argument
159 if (msr == MSR_APICBASE) { in lapic_rdmsr()
163 offset = x2apic_msr_to_regoff(msr); in lapic_rdmsr()
171 lapic_wrmsr(struct vcpu *vcpu, u_int msr, uint64_t val, bool *retu) in lapic_wrmsr() argument
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/freebsd/sys/x86/x86/
H A Dx86_mem.c202 int i, j, msr; in x86_mrfetch() local
208 msr = MSR_MTRR64kBase; in x86_mrfetch()
209 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { in x86_mrfetch()
210 msrv = rdmsr(msr); in x86_mrfetch()
220 msr = MSR_MTRR16kBase; in x86_mrfetch()
221 for (i = 0; i < MTRR_N16K / 8; i++, msr++) { in x86_mrfetch()
222 msrv = rdmsr(msr); in x86_mrfetch()
232 msr = MSR_MTRR4kBase; in x86_mrfetch()
233 for (i = 0; i < MTRR_N4K / 8; i++, msr++) { in x86_mrfetch()
234 msrv = rdmsr(msr); in x86_mrfetch()
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/freebsd/sys/arm64/arm64/
H A Dlocore.S71 msr contextidr_el1, xzr
123 msr sp_el0, x15
233 msr daifset, #DAIF_INTR
239 msr contextidr_el1, xzr
279 msr sp_el0, x15
283 msr ttbr0_el1, x27
297 msr tpidr_el1, x18
320 msr sctlr_el1, x2
331 msr spsr_el1, x2
332 msr elr_el1, lr
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H A Dswtch.S44 msr mdscr_el1, \tmp
53 msr mdscr_el1, \tmp
69 msr contextidr_el1, x10
109 msr sp_el0, x19
119 msr tpidr_el0, x6
121 msr tpidrro_el0, x6
191 msr sp_el0, x20
214 msr tpidr_el0, x6
216 msr tpidrro_el0, x6
239 msr daifset, #(DAIF_D | DAIF_INTR)
[all …]
H A Dexception.S84 msr sp_el0, x1
101 msr daifclr, #(DAIF_D | DAIF_A)
108 msr daifclr, #(DAIF_A)
117 msr daifset, #(DAIF_ALL)
136 msr sp_el0, x18
138 msr spsr_el1, x11
139 msr elr_el1, x10
179 msr daifset, #(DAIF_INTR)
189 msr daif, x19
/freebsd/sys/arm64/vmm/
H A Dvmm_nvhe_exception.S72 msr vbar_el2, x6
77 msr vttbr_el2, x9
79 msr ttbr0_el2, x0
87 msr mair_el2, x9
89 msr tcr_el2, x2
92 msr sctlr_el2, x3
94 msr vtcr_el2, x4
110 msr vbar_el2, x1
116 msr sctlr_el2, x2
/freebsd/sys/powerpc/ofw/
H A Dofwcall32.S40 .long 0, 0, 0, 0, 0 /* msr/sprg0-3 used in Open Firmware */
64 /* Record the old MSR */
79 * Set the MSR to the OF value. This has the side effect of disabling
91 * top of the stack along with the old MSR so we can get them back
99 stw %r6,28(%r1) /* Save old MSR */
108 /* Reload stack pointer and MSR from the OFW stack */
113 /* Now set the real MSR */
140 /* Record the old MSR to real-mode-accessible area */
149 /* Set the MSR to the RTAS value */
166 /* Now set the MSR back */
H A Dofwcall64.S47 .llong 0, 0, 0, 0, 0 /* msr/sprg0-3 used in Open Firmware */
74 * at most 32 bits wide: lr, cr, r2, r13-r31, the old MSR. These
100 /* Record the old MSR */
114 * Set the MSR to the OF value. This has the side effect of disabling
133 * the old MSR so we can get them back later.
139 std %r6,24(%r1) /* Save old MSR */
169 /* Reload stack pointer, MSR, and reference PC from the OFW stack */
175 /* Get back to the MSR/PC we want, using the cached high bits of PC */
234 * at most 32 bits wide: lr, cr, r2, r13-r31, the old MSR. These
260 /* Record the old MSR */
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/freebsd/sys/powerpc/cpufreq/
H A Dpcr.c107 register_t msr; in write_scom() local
112 msr = mfmsr(); in write_scom()
113 mtmsr(msr & ~PSL_EE); isync(); in write_scom()
126 mtmsr(msr); isync(); in write_scom()
132 register_t msr; in read_scom() local
135 msr = mfmsr(); in read_scom()
136 mtmsr(msr & ~PSL_EE); isync(); in read_scom()
146 mtmsr(msr); isync(); in read_scom()
262 register_t pcr, msr; in pcr_set() local
280 msr = mfmsr(); in pcr_set()
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/freebsd/sys/dev/hyperv/vmbus/aarch64/
H A Dhyperv_machdep.h52 void arm_hv_set_vreg(u32 msr, u64 val);
53 #define WRMSR(msr, val) arm_hv_set_vreg(msr, val) argument
54 u64 arm_hv_get_vreg(u32 msr);
55 #define RDMSR(msr) arm_hv_get_vreg(msr) argument
H A Dhyperv_machdep.c51 arm_hv_set_vreg(u32 msr, u64 value) in arm_hv_set_vreg() argument
56 HV_PARTITION_ID_SELF, HV_VP_INDEX_SELF, msr, 0, value, NULL); in arm_hv_set_vreg()
60 hv_get_vpreg_128(u32 msr, struct hv_get_vp_registers_output *result) in hv_get_vpreg_128() argument
70 args.a4 = msr; in hv_get_vpreg_128()
83 arm_hv_get_vreg(u32 msr) in arm_hv_get_vreg() argument
87 hv_get_vpreg_128(msr, &output); in arm_hv_get_vreg()
/freebsd/sys/arm64/include/
H A Dcpufunc.h51 "msr daifset, #(" __XSTRING(DAIF_D) ") \n" in dbg_disable()
61 __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_D) ")"); in dbg_enable()
72 "msr daifset, #(" __XSTRING(DAIF_INTR) ") \n" in intr_disable()
89 __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_INTR) ")"); in intr_enable()
96 __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_A) ")"); in serror_enable()
135 "msr ttbr0_el1, %0 \n" in set_ttbr0()
165 "msr s0_3_c1_c0_0, %0\n" in wfet()
175 "msr s0_3_c1_c0_1, %0\n" in wfit()
/freebsd/sys/amd64/vmm/intel/
H A Dvmx_msr.h54 * This pretty much limits us to configuring the MSR bitmap before VMCS
64 int msr_bitmap_change_access(char *bitmap, u_int msr, int access);
66 #define guest_msr_rw(vmx, msr) \ argument
67 msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_RW)
69 #define guest_msr_ro(vmx, msr) \ argument
70 msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_READ)
H A Dvmx_msr.c125 "correct value of ctl bit %d for msr " in vmx_set_ctlreg()
126 "0x%0x and true msr 0x%0x", i, ctl_reg, in vmx_set_ctlreg()
143 msr_bitmap_change_access(char *bitmap, u_int msr, int access) in msr_bitmap_change_access() argument
147 if (msr <= 0x00001FFF) in msr_bitmap_change_access()
148 byte = msr / 8; in msr_bitmap_change_access()
149 else if (msr >= 0xC0000000 && msr <= 0xC0001FFF) in msr_bitmap_change_access()
150 byte = 1024 + (msr - 0xC0000000) / 8; in msr_bitmap_change_access()
154 bit = msr & 0x7; in msr_bitmap_change_access()
305 * in this MSR are valid. in vmx_msr_init()
327 * Initialize guest IA32_PAT MSR with default value after reset. in vmx_msr_guest_init()
[all …]
/freebsd/sys/powerpc/booke/
H A Dmp_cpudep.c53 uint32_t msr, csr; in cpudep_ap_bootstrap() local
69 /* Set MSR */ in cpudep_ap_bootstrap()
71 msr = PSL_CM | PSL_ME; in cpudep_ap_bootstrap()
73 msr = PSL_ME; in cpudep_ap_bootstrap()
75 mtmsr(msr); in cpudep_ap_bootstrap()
/freebsd/sys/contrib/edk2/Include/Library/
H A DBaseLib.h5743 Returns the lower 32-bits of a Machine Specific Register(MSR).
5745 Reads and returns the lower 32-bits of the MSR specified by Index.
5751 @param Index The 32-bit MSR index to read.
5753 @return The lower 32 bits of the MSR identified by Index.
5764 Writes a 32-bit value to a Machine Specific Register(MSR), and returns the value.
5765 The upper 32-bits of the MSR are set to zero.
5767 Writes the 32-bit value specified by Value to the MSR specified by Index. The
5768 upper 32-bits of the MSR write are set to zero. The 32-bit value written to
5769 the MSR is returned. No parameter checking is performed on Index or Value,
5774 @param Index The 32-bit MSR index to write.
[all …]

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