| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | msi.txt | 4 Message Signaled Interrupts (MSIs) are a class of interrupts generated by a
7 MSIs were originally specified by PCI (and are used with PCIe), but may also be
12 MSIs are distinguished by some combination of:
57 MSI clients are devices which generate MSIs. For each MSI they wish to
67 This property is unordered, and MSIs may be allocated from any combination of
70 If a device has restrictions on the allocation of MSIs, these restrictions
75 and the set of MSIs they can potentially generate.
112 /* Can only generate MSIs to msi_a */
121 * Can generate MSIs to either A or B.
131 * Can generate MSIs to all of the MSI controllers.
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| H A D | marvell,ap806-sei.yaml | 18 and is wired while a second set comes from the CPs by the mean of MSIs.
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_irq_kms.c | 234 * MSIs should be enabled on a particular chip (all asics).
235 * Returns true if MSIs should be enabled, false if MSIs
244 /* MSIs don't work on AGP */ in radeon_msi_ok()
250 * of address for "64-bit" MSIs which breaks on some platforms, notably in radeon_msi_ok()
265 /* HP RS690 only seems to work with MSIs. */ in radeon_msi_ok()
271 /* Dell RS690 only seems to work with MSIs. */ in radeon_msi_ok()
277 /* Dell RS690 only seems to work with MSIs. */ in radeon_msi_ok()
283 /* Gateway RS690 only seems to work with MSIs. */ in radeon_msi_ok()
289 /* try and enable MSIs by default on all RS690s */ in radeon_msi_ok()
300 /* APUs work fine with MSIs */ in radeon_msi_ok()
[all …]
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| /linux/drivers/iommu/riscv/ |
| H A D | iommu-platform.c | 33 "uh oh, the IOMMU can't send MSIs to 0x%llx, sending to 0x%llx instead\n", in riscv_iommu_write_msi_msg()
90 dev_warn(dev, "failed to allocate MSIs\n"); in riscv_iommu_platform_probe()
103 dev_info(dev, "using MSIs\n"); in riscv_iommu_platform_probe()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | apple,pcie.yaml | 30 MSIs are handled by the PCIe controller and translated into regular
31 interrupts. A range of 32 MSIs is provided. These 32 MSIs can be
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| /linux/arch/powerpc/platforms/pseries/ |
| H A D | msi.c | 90 pr_debug("rtas_msi: Setting MSIs to 0 failed!\n"); in rtas_disable_msi()
133 pr_debug("rtas_msi: %s requests < %d MSIs\n", prop_name, nvec); in check_req()
310 * use the remainder as spare MSIs for anyone that wants them. */ in msi_quota_for_device()
333 * fact that we using RTAS for MSIs, we don't have the 32 bit MSI RTAS in rtas_hack_32bit_msi_gen2()
655 pr_err("PCI: failed to find MSIs for bridge %pOF (domain %d)\n", in pseries_msi_allocate_domains()
675 /* No LSI -> leave MSIs (if any) configured */ in rtas_msi_pci_irq_fixup()
681 /* No MSI -> MSIs can't have been assigned by fw, leave LSI */ in rtas_msi_pci_irq_fixup()
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| /linux/Documentation/arch/powerpc/ |
| H A D | pci_iov_resource_on_powernv.rst | 24 partitions (i.e., filtering of DMA, MSIs etc.) and to provide a mechanism
33 return all 1's value. MSIs are also blocked. There's a bit more state that
52 For DMA, MSIs and inbound PCIe error messages, we have a table (in
63 - For MSIs, we have two windows in the address space (one at the top of
91 reserved for MSIs but this is not a problem at this point; we just
152 "master PE" which is the one used for DMA, MSIs, etc., and "secondary
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| /linux/drivers/irqchip/ |
| H A D | irq-loongson-pch-msi.c | 26 u32 irq_first; /* The vector number that MSIs starts */
27 u32 num_irqs; /* The number of vectors for MSIs */
199 pr_debug("Registering %d MSIs, starting at %d\n", in pch_msi_init()
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| H A D | irq-gic-v3-its-msi-parent.c | 74 * minimum of 32 MSIs for DevID 0. If you want more because all in its_pci_msi_prepare()
143 /* Allocate at least 32 MSIs, and always as a power of 2 */ in its_pmsi_prepare()
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| H A D | irq-alpine-msi.c | 34 u32 spi_first; /* The SGI number that MSIs start */
35 u32 num_spis; /* The number of SGIs for MSIs */
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| H A D | irq-sg2042-msi.c | 31 * @irq_first: First vectors number that MSIs starts
32 * @num_irqs: Number of vectors for MSIs
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| H A D | irq-gic-v3-its-fsl-mc-msi.c | 63 /* Allocate at least 32 MSIs, and always as a power of 2 */ in its_fsl_mc_msi_prepare()
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| H A D | irq-gic-v2m.c | 70 u32 spi_start; /* The SPI number that MSIs start */
71 u32 nr_spis; /* The number of SPIs for MSIs */
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| /linux/arch/x86/platform/uv/ |
| H A D | uv_irq.c | 120 * on the specified blade to allow the sending of MSIs to the specified CPU.
130 * Disable the specified MMR located on the specified blade so that MSIs are
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| /linux/include/asm-generic/ |
| H A D | msi.h | 34 /* Device generating MSIs is proxying for another device */
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| /linux/Documentation/virt/kvm/devices/ |
| H A D | mpic.rst | 30 MSIs may be signaled by using this attribute group to write
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| /linux/Documentation/accel/qaic/ |
| H A D | qaic.rst | 21 non-empty and generate MSIs at a rate equivalent to the speed of the
24 MSIs per second. It has been observed that most systems cannot tolerate this
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| /linux/drivers/iommu/intel/ |
| H A D | irq_remapping.c | 498 /* Block compatibility-format MSIs */ in iommu_enable_irq_remapping()
1290 * With posted MSIs, the MSI vectors are multiplexed into a single notification
1292 * MSIs are then dispatched in a demux loop that harvests the MSIs from the
1293 * CPU's Posted Interrupt Request bitmap. I.e. Posted MSIs never get sent to
1300 * For the example below, 3 MSIs are coalesced into one CPU notification. Only
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| /linux/include/uapi/linux/ |
| H A D | vfio_zdev.h | 50 __u16 noi; /* Maximum number of MSIs */
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| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | brcm,iproc-flexrm-mbox.txt | 15 The FlexRM engine will send MSIs (instead of wired
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| /linux/drivers/pci/msi/ |
| H A D | msi.c | 23 * @nvec: how many MSIs have been requested?
41 * You can't ask to have 0 or less MSIs configured. in pci_msi_supported()
295 /* Lies, damned lies, and MSIs */ in msi_setup_msi_desc()
346 /* All MSIs are unmasked by default; mask them all */ in __msi_capability_init()
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| /linux/drivers/cdx/controller/ |
| H A D | mcdi_functions.h | 113 * cdx_mcdi_msi_enable - Enable/Disable MSIs for cdx device represented
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| /linux/arch/x86/include/asm/ |
| H A D | irq_vectors.h | 101 * Posted interrupt notification vector for all device MSIs delivered to
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| /linux/tools/perf/trace/beauty/arch/x86/include/asm/ |
| H A D | irq_vectors.h | 101 * Posted interrupt notification vector for all device MSIs delivered to
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| /linux/drivers/parisc/ |
| H A D | iosapic.c | 30 ** to a processor write to memory or MMIO. MSIs can be generated by I/O
34 ** MSIs (e.g. GSC or HP-PB) or convert line based interrupts into MSIs
35 ** (e.g. PCI and EISA). IA64 supports MSIs via a "local SAPIC" which
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