| /illumos-gate/usr/src/uts/sun4/io/px/ |
| H A D | px_ioapi.h | 236 * MSI Definitions
238 * MSI - Message Signaled Interrupt
242 * A device signals an interrupt via MSI using a posted
245 * The MSI capability data structure contains fields for
247 * sending an MSI message on the bus. MSI-X is an extended
248 * form of MSI, but uses the same mechanism for signaling
249 * the interrupt as MSI. For the purposes of this document,
250 * the term "MSI" refers to MSI or MSI-X.
252 * Root complexes that support MSI define an address range
255 * SUN4V/pci requirements for MSI:
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| H A D | px_msi.h | 34 * MSI data structure.
37 dev_info_t *msi_dip; /* MSI consumer dip */
39 uint_t msi_state; /* MSI alloc state */
40 msinum_t msi_msinum; /* MSI number */
48 * MSI soft state structure.
52 msinum_t msi_1st_msinum; /* First MSI number */
53 uint_t msi_data_mask; /* MSI data mask */
54 uint_t msi_data_width; /* MSI data width */
55 uint64_t msi_addr32; /* MSI 32 address */
56 uint64_t msi_addr32_len; /* MSI 32 length */
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| H A D | px_msi.c | 63 * Check for all MSI related properties and in px_msi_attach()
145 * MSI interrupts are allocated as contiguous ranges at in px_msi_alloc()
146 * power of 2 boundaries from the start of the MSI array. in px_msi_alloc()
167 "Retry MSI allocation with new msi_count " in px_msi_alloc()
192 * MSI-X interrupts are allocated from the end of the MSI in px_msi_alloc()
256 * Find and release the specified MSI/X numbers. in px_msi_free()
259 * a full linear search of the MSI/X table looking for MSI/X in px_msi_free()
277 /* Fail if the MSI/X numbers were not found */ in px_msi_free()
305 "inum 0x%x msi 0x%x\n", inum, *msi_num_p); in px_msi_get_msinum()
314 "no msi for inum 0x%x\n", inum); in px_msi_get_msinum()
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| H A D | px_msiq.c | 68 * Around 90% of available MSIQs are reserved for the MSI/Xs. in px_msiq_attach()
404 /* #msi-eqs */ in px_msiq_get_props()
406 DDI_PROP_DONTPASS, "#msi-eqs", 0); in px_msiq_get_props()
410 /* msi-eq-size */ in px_msiq_get_props()
412 DDI_PROP_DONTPASS, "msi-eq-size", 0); in px_msiq_get_props()
420 /* msi-eq-to-devino: msi-eq#, devino# fields */ in px_msiq_get_props()
422 DDI_PROP_DONTPASS, "msi-eq-to-devino", (caddr_t)&valuep, &length); in px_msiq_get_props()
426 * On sun4u PCIe systems, the msi-eq-to-devino property is broken and in px_msiq_get_props()
427 * these systems defines this property as msi-eq-devino. in px_msiq_get_props()
430 DBG(DBG_MSIQ, px_p->px_dip, "msi-eq-to-devino is not found\n"); in px_msiq_get_props()
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| H A D | px_tools.c | 136 if ((iget->msi < msi_state_p->msi_1st_msinum) || in pxtool_get_intr()
137 (iget->msi >= (msi_state_p->msi_1st_msinum + in pxtool_get_intr()
144 if ((px_lib_msi_getvalid(dip, iget->msi, in pxtool_get_intr()
149 if (px_lib_msi_getmsiq(dip, iget->msi, in pxtool_get_intr()
155 iget->msi = (uint32_t)-1; in pxtool_get_intr()
212 iget->msi, &iget->num_devs_ret, iget->dev); in pxtool_get_intr()
296 if ((iset.msi < msi_state_p->msi_1st_msinum) || in pxtool_set_intr()
297 (iset.msi >= (msi_state_p->msi_1st_msinum + in pxtool_set_intr()
304 if ((px_lib_msi_getvalid(dip, iset.msi, in pxtool_set_intr()
309 if (px_lib_msi_getmsiq(dip, iset.msi, in pxtool_set_intr()
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| /illumos-gate/usr/src/man/man8/ |
| H A D | pcitool.8 | 42 .Fl m Ar msi# Ns | Ns Cm all
50 On x86 platforms, both INOs and MSI/Xs are mapped to the same interrupt vectors.
53 option to retrieve and reroute any interrupt vectors (both INO and MSI/Xs).
56 more MSI/Xs are mapped to an INO.
57 So, INO and MSI/Xs are individually retargetable.
62 option for MSI/Xs.
73 On some platforms (such as x86) multiple MSI interrupts of a single function
79 works only on supported platforms and only for groups of MSI interrupts.
90 Display device and CPU routing information for MSI/Xs on a given nexus,
91 or reroute the given MSI/X or MSI/X group to a specific CPU.
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| /illumos-gate/usr/src/man/man9f/ |
| H A D | ddi_intr_dup_handler.9f | 8 ddi_intr_dup_handler \- reuse interrupt handler and arguments for MSI-X
51 The \fBddi_intr_dup_handler()\fR function is a feature for MSI-X interrupts
53 initialized or added primary MSI-X interrupt vector in order to share the same
57 For example, if 2 MSI-X interrupts were allocated to a driver and 32 interrupts
90 Before removing the original MSI-X interrupt handler, all dup-ed interrupt
91 handlers associated with this MSI-X interrupt must have been disabled and
121 not to support MSI-X interrupts.
146 * 1 MSI-X to use and then dup the rest.
150 cmn_err(CE_WARN, "Failed to retrieve the MSI-X interrupt count");
157 /* Allocate one MSI-X interrupt handle */
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| H A D | ddi_intr_alloc.9f | 120 is the relative interrupt vector number, from \fB0\fR to \fB31\fR for MSI, from
121 \fB0\fR to \fB2047\fR for MSI-X. The first interrupt vector is \fB0\fR. The
122 last relative vector is \fB31\fR for MSI or \fB2047\fR for MSI-X.
129 If MSI interrupts are being allocated, the \fIcount\fR argument passed should
242 If a device driver that uses \fBMSI\fR and \fBMSI-X\fR interrupts resets the
244 reset could cause a device driver to lose any \fBMSI\fR and \fBMSI-X\fR
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| H A D | ddi_intr_enable.9f | 121 \fBddi_intr_block_enable()\fR function is useful for enabling MSI interrupts
152 \fBddi_intr_block_disable()\fR function is useful for disabling MSI interrupts
228 If a device driver that uses \fBMSI\fR and \fBMSI-X\fR interrupts resets the
230 reset could cause a device driver to lose any \fBMSI\fR and \fBMSI-X\fR
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| H A D | ddi_intr_add_handler.9f | 204 .Sy MSI
206 .Sy MSI-X
210 .Sy MSI
212 .Sy MSI-X
221 pointer to its softstate and the second argument as the value of the MSI vector.
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| /illumos-gate/usr/src/uts/common/io/ |
| H A D | pci_intr_lib.c | 28 * Support for MSI, MSIX and INTx
40 * MSI-X BIR Index Table:
102 * Helper function that returns with 'cfg_hdl', MSI/X ctrl pointer,
103 * and caps_ptr for MSI/X if these are found.
125 DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: MSI " in pci_get_msi_ctrl()
137 DDI_INTR_NEXDBG((CE_CONT, "pci_get_msi_ctrl: MSI-X " in pci_get_msi_ctrl()
152 * Get the capabilities of the MSI/X interrupt
178 /* MSI-X supports PVM, 64bit by default */ in pci_msi_get_cap()
195 * Configure address/data and number MSI/Xs fields in the MSI/X
252 /* Offset into the "inum"th entry in the MSI-X table */ in pci_msi_configure()
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| /illumos-gate/usr/src/uts/common/io/scsi/adapters/smrt/ |
| H A D | smrt_interrupts.c | 23 return ("MSI-X"); in smrt_interrupt_type_name()
25 return ("MSI"); in smrt_interrupt_type_name()
41 * which all share the same PCI device ID, then we default to MSI. in smrt_try_msix()
52 * broken MSI support on at least one controller. We could in smrt_try_msix()
53 * blindly try MSI-X everywhere, except that on at least some in smrt_try_msix()
54 * 6.XX firmware versions, MSI-X interrupts do not appear in smrt_try_msix()
58 * For now, assume we should try for MSI-X with all 8.XX in smrt_try_msix()
61 dev_err(smrt->smrt_dip, CE_NOTE, "!trying MSI-X interrupts " in smrt_try_msix()
186 * line with entirely defective MSI support. The specification is in smrt_interrupts_setup()
187 * somewhat unclear on the precise nature of MSI-X support with Smart in smrt_interrupts_setup()
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| /illumos-gate/usr/src/uts/common/sys/ |
| H A D | ddi_intr_impl.h | 93 * The following 3 members are used to support MSI-X specific features
96 uint_t ih_dup_cnt; /* # of dupped msi-x vectors */
144 #define DDI_INTR_MSIX_DUP 0x01 /* MSI-X vector which has been dupped */
146 /* Maximum number of MSI resources to allocate */
149 /* Default number of MSI-X resources to allocate */
189 * One such data structure is allocated for MSI-X enabled
190 * device. If no MSI-X is enabled then it is NULL
193 /* MSI-X Table related information */
194 ddi_acc_handle_t msix_tbl_hdl; /* MSI-X table handle */
195 uint32_t *msix_tbl_addr; /* MSI-X table addr */
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| H A D | pci.h | 615 #define PCI_CAP_ID_MSI 0x5 /* MSI supported */
627 #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */
915 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
917 #define PCI_MSI_CTRL 0x02 /* MSI control register, 2 bytes */
918 #define PCI_MSI_ADDR_OFFSET 0x04 /* MSI 32-bit msg address, 4 bytes */
919 #define PCI_MSI_32BIT_DATA 0x08 /* MSI 32-bit msg data, 2 bytes */
920 #define PCI_MSI_32BIT_EXTDATA 0x0A /* MSI 32-bit msg ext data, 2 bytes */
921 #define PCI_MSI_32BIT_MASK 0x0C /* MSI 32-bit mask bits, 4 bytes */
922 #define PCI_MSI_32BIT_PENDING 0x10 /* MSI 32-bit pending bits, 4 bytes */
925 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
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| /illumos-gate/usr/src/uts/intel/io/vmm/io/ |
| H A D | ppt.c | 70 * If the MSI-X table is located in the middle of a BAR then that MMIO
71 * region gets split into two segments - one segment above the MSI-X table
72 * and the other segment below the MSI-X table - with a hole in place of
73 * the MSI-X table so accesses to it can be trapped and emulated.
113 } msi; member
933 if (ppt->msi.num_msgs == 0) in ppt_teardown_msi()
936 for (i = 0; i < ppt->msi.num_msgs; i++) { in ppt_teardown_msi()
939 (void) ddi_intr_get_cap(ppt->msi.inth[i], &intr_cap); in ppt_teardown_msi()
941 ddi_intr_block_disable(&ppt->msi.inth[i], 1); in ppt_teardown_msi()
943 ddi_intr_disable(ppt->msi.inth[i]); in ppt_teardown_msi()
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| /illumos-gate/usr/src/uts/i86xpv/io/psm/ |
| H A D | xpv_intr.c | 45 /* Multiple vector support for MSI */
48 /* Multiple vector support for MSI-X */
52 * check whether the system supports MSI
55 * Since MSI is required for PCI-E system, it returns PSM_SUCCESS
56 * to indicate this system supports MSI.
87 /* MSI is not supported on this system */ in apic_check_msi_support()
233 * Set the address/data fields in the MSI/X capability structure
234 * XXX: MSI-X support
253 /* MSI Address */ in apic_pci_msi_enable_vector()
259 /* MSI Data: MSI is edge triggered according to spec */ in apic_pci_msi_enable_vector()
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| /illumos-gate/usr/src/cmd/pcitool/ |
| H A D | pcitool_usage.c | 75 " %s pci@<unit-address> -m <msi#> | all",
175 "-m <[cpu#],msi#> changes or retrieves current interrupts information of given",
176 " nexus and given MSI/X. The special value of 'all' can be used to select",
177 " all MSI/Xs.",
182 " Note: On x86 platforms, both INOs and MSI/Xs are mapped to the same",
184 " vectors (both INO and MSI/Xs). So, -m option is not required on x86",
187 " A specific INO or MSI/X must be selected if -w specified.",
189 "-w <cpu#> [ -g ] to change an INO or MSI/X <->CPU binding.",
191 " Note: On certain platforms (e.g. X86), multiple MSI interrupts of a single",
193 " supported platforms and only for groups of MSI interrupts. When -g is",
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| /illumos-gate/usr/src/uts/common/io/cxgbe/firmware/ |
| H A D | t4fw_cfg.txt | 26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
41 # to allow for this. And because of the MSI-X resource allocation
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
159 # NMSIX = 1088 # available MSI-X Vectors
170 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
174 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
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| H A D | t6fw_cfg.txt | 25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
211 # NMSIX = 1088 # available MSI-X Vectors
222 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
226 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
234 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
241 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
248 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
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| H A D | t5fw_cfg.txt | 25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
194 # NMSIX = 1088 # available MSI-X Vectors
205 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
209 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
217 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
224 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
231 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
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| /illumos-gate/usr/src/cmd/bhyve/common/ |
| H A D | pci_passthru.c | 92 len = 10; /* minimum length of msi capability */ in msi_caplen()
99 * Ignore the 'mask' and 'pending' bits in the MSI capability. in msi_caplen()
194 * Copy the msi capability structure in the last 16 bytes of the in passthru_add_msicap()
213 /* Reduce the number of MSI vectors if higher than OS limit */ in passthru_intr_limit()
233 /* Reduce the number of MSI-X vectors if higher than OS limit */ in passthru_intr_limit()
253 * Parse the capabilities and cache the location of the MSI in cfginitmsi()
254 * and MSI-X capabilities. in cfginitmsi()
263 * Copy the MSI capability into the config in cfginitmsi()
281 * Copy the MSI-X capability in cfginitmsi()
315 /* Allocate the emulated MSI-X table array */ in cfginitmsi()
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| /illumos-gate/usr/src/uts/common/io/i40e/ |
| H A D | i40e_intr.c | 48 * o Extended Message Signaled Interrupts (MSI-X)
49 * o Message Signaled Interrupts (MSI)
52 * Generally speaking the hardware logically handles MSI and INTx the same and
54 * case. With MSI-X available, each physical function of the device provides the
62 * interrupts is always bound to MSI-X vector zero. Next, we spread out all of
71 * The hardware provides the means of mapping various queues to MSI-X interrupts
94 * any MSI-X to the system. In such a world, there is only one transmit/receive
102 * QINT_TQCTL and QINT_RQCTL registers have a field, 'MSI-X 0 index' which
110 * end up enabling it on the queue registers rather than on the MSI-X registers.
111 * In the MSI-X world, because they can be enabled and disabled, this is
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| /illumos-gate/usr/src/uts/i86pc/io/pcplusmp/ |
| H A D | apic_introp.c | 54 * Set the address/data fields in the MSI/X capability structure
55 * XXX: MSI-X support
97 /* MSI Address */ in apic_pci_msi_enable_vector()
100 /* MSI Data: MSI is edge triggered according to spec */ in apic_pci_msi_enable_vector()
135 /* Offset into the "inum"th entry in the MSI-X table */ in apic_pci_msi_enable_vector()
187 * Finds "count" contiguous MSI vectors starting at the proper alignment
209 * allocated MSI vectors and is used to calculate the aligned in apic_find_multi_vectors()
389 /* for MSI/X only */ in apic_free_vectors()
438 /* Offset into "inum"th entry in the MSI-X table & clear mask */ in apic_pci_msi_enable_mode()
474 /* Fail if this is an MSI intr and is part of a group. */ in apic_set_cpu()
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| /illumos-gate/usr/src/test/util-tests/tests/pcieadm/ |
| H A D | pcieadmtest.ksh | 141 show-cfgspace -f /dev/stdin ht.msi
143 show-cfgspace -f /dev/stdin ht.msi.command
146 pcieadm_validate_output bridge.pci bridge-ht.msi-p.out 1 \
147 show-cfgspace -p -o value,short -f /dev/stdin ht.msi
148 pcieadm_validate_output bridge.pci bridge-ht.msi.command-p.out 0 \
149 show-cfgspace -p -o value,short -f /dev/stdin ht.msi.command
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| /illumos-gate/usr/src/uts/common/io/usb/hcd/xhci/ |
| H A D | xhci_intr.c | 30 * speaking, interrupts for MSI and MSI-X are directed to a specific vector for
36 * quirks here is that when we acknowledge the PCI level MSI or MSI-X, the IP
168 * Note that when using MSI and MSI-X, writing to various PCI registers in xhci_intr()
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