| /freebsd/sys/x86/x86/ |
| H A D | msi.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
16 * 3. Neither the name of the author nor the names of any co-contributors
34 * Support for PCI Message Signalled Interrupts (MSI). MSI interrupts on
63 /* Fields in address for Intel MSI messages. */
72 /* Fields in data for Intel MSI messages. */
89 * Build Intel MSI message and data values from a source. AMD64 systems
92 #define INTEL_ADDR(msi) \ argument
93 (MSI_INTEL_ADDR_BASE | (msi)->msi_cpu << 12 | \
95 #define INTEL_DATA(msi) \ argument
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| /freebsd/share/man/man9/ |
| H A D | pci.9 | 223 function is used to modify the value of a register in the PCI-express
242 function is used to read the value of a register in the PCI-express
255 to a register in the PCI-express capability register set of device
288 .Bd -literal -offset indent
359 function is used to locate the first instance of a PCI-express
375 PCI-express device,
380 function is used to locate the next instance of a PCI-express
434 function walks up the PCI device hierarchy to locate the PCI-express root
449 .Bl -hang -width ".Dv PCI_ID_RID"
453 Read the MSI routing ID.
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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| H A D | layerscape-pcie-gen4.txt | 4 the common properties defined in mobiveil-pcie.txt.
7 - compatible: should contain the platform identifier such as:
8 "fsl,lx2160a-pcie"
9 - reg: base addresses and lengths of the PCIe controller register blocks.
12 - interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14 - interrupt-names: It could include the following entries:
17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
20 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
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| /freebsd/sys/dev/cxgbe/firmware/ |
| H A D | t5fw_cfg_fpga.txt | 3 # Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
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| H A D | t4fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
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| H A D | t6fw_cfg_fpga.txt | 3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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| H A D | t5fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 4-port T5-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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| H A D | t6fw_cfg_uwire.txt | 3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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| H A D | t4fw_cfg.txt | 46 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
96 # PF4 is the resource-rich PF that the bus/nexus driver attaches to.
97 # It gets 32 MSI/128 MSI-X vectors.
130 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
136 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
|
| H A D | t6fw_cfg_hashfilter.txt | 79 mc_mode_brc[0] = 0 # mc0 - 1: enable BRC, 0: enable RBC
81 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
131 # PF4 is the resource-rich PF that the bus/nexus driver attaches to.
132 # It gets 32 MSI/128 MSI-X vectors.
157 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
163 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
|
| H A D | t5fw_cfg.txt | 30 # minus 128-entries for FL and HP
83 mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
84 mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC
90 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
140 # PF4 is the resource-rich PF that the bus/nexus driver attaches to.
141 # It gets 32 MSI/128 MSI-X vectors.
175 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
181 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
|
| H A D | t5fw_cfg_hashfilter.txt | 30 # minus 128-entries for FL and HP
92 mc_mode_brc[0] = 0 # mc0 - 1: enable BRC, 0: enable RBC
93 mc_mode_brc[1] = 0 # mc1 - 1: enable BRC, 0: enable RBC
99 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
149 # PF4 is the resource-rich PF that the bus/nexus driver attaches to.
150 # It gets 32 MSI/128 MSI-X vectors.
178 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
184 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
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| H A D | t6fw_cfg.txt | 86 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
88 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
138 # PF4 is the resource-rich PF that the bus/nexus driver attaches to.
139 # It gets 32 MSI/128 MSI-X vectors.
175 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
181 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
|
| /freebsd/sys/dev/pci/ |
| H A D | pci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
238 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
241 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */
255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
256 * or the CMIC-SL (AKA ServerWorks GC_LE).
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| /freebsd/sys/amd64/vmm/io/ |
| H A D | ppt.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 * If the MSI-X table is located in the middle of a BAR then that MMIO
60 * region gets split into two segments - one segment above the MSI-X table
61 * and the other segment below the MSI-X table - with a hole in place of
62 * the MSI-X table so accesses to it can be trapped and emulated.
68 MALLOC_DEFINE(M_PPTMSIX, "pptmsix", "Passthru MSI-X resources");
94 } msi; member
133 * - be allowed by administrator to be used in this role in ppt_probe()
134 * - be an endpoint device in ppt_probe()
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_pcie_w_reg.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
376 * - If MSI-X is enabled and auto_clear control bit =TRUE, automatically
377 * cleared after MSI-X message associated with this specific interrupt
378 * bit is sent (MSI-X acknowledge is received).
379 * - Software can set a bit in this register by writing 1 to the
381 * Write-0 clears a bit. Write-1 has no effect.
382 * - On CPU Read - If clear_on_read control bit =TRUE, automatically
400 * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X
408 * Used when auto-mask control bit=True. Enables CPU to clear a specific
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| /freebsd/sys/arm/arm/ |
| H A D | gic.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
104 ((_sc->typer & GICD_TYPER_SECURITYEXT) == GICD_TYPER_SECURITYEXT)
117 /* be used for MSI/MSI-X interrupts */
119 /* for a MSI/MSI-X interrupt */
127 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
131 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)
137 { -1, 0 }
153 bus_read_4((_sc)->gic_res[GIC_RES_CPU], (_reg))
155 bus_write_4((_sc)->gic_res[GIC_RES_CPU], (_reg), (_val))
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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| H A D | marvell,mpic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
16 On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
18 Provides MSI handling for the PCIe controllers.
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| /freebsd/share/man/man4/ |
| H A D | vmx.4 | 28 .Bd -ragged -offset indent
36 .Bd -literal -offset indent
61 checksum offloading, MSI/MSI-X support and hardware VLAN tagging in
70 .Bl -bullet -compact -offset indent
88 The number of queues allocated depends on the presence of MSI-X,
92 does not enable MSI-X support on VMware by default.
95 tunable must be disabled to enable MSI-X support.
101 .Bl -tag -width indent
103 .It Va hw.vmx. Ns Ar X Ns Va .txnqueue
108 .It Va hw.vmx. Ns Ar X Ns Va .rxnqueue
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| /freebsd/sys/dev/ntb/ntb_hw/ |
| H A D | ntb_hw_amd.c | 1 /*-
46 * The Non-Transparent Bridge (NTB) is a device that allows you to connect
47 * two or more systems using a PCI-e links, providing remote memory access.
89 .desc = "AMD Non-Transparent Bridge"},
99 .desc = "AMD Non-Transparent Bridge"},
109 .desc = "Hygon Non-Transparent Bridge"},
115 PCI_DESCR("AMD Non-Transparent Bridge") },
118 PCI_DESCR("AMD Non-Transparent Bridge") },
121 PCI_DESCR("Hygon Non-Transparent Bridge") }
126 &g_amd_ntb_hw_debug_level, 0, "amd_ntb_hw log level -- higher is verbose");
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| /freebsd/sys/arm/annapurna/alpine/ |
| H A D | alpine_pci_msix.c | 1 /*-
48 #define ERR_NOT_IN_MAP -1
66 {"annapurna-labs,al-msix", true},
67 {"annapurna-labs,alpine-msix", true},
120 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) in al_msix_probe()
123 device_set_desc(dev, "Annapurna-Labs MSI-X Controller"); in al_msix_probe()
146 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); in al_msix_attach()
147 if (sc->res == NULL) { in al_msix_attach()
152 sc->base_addr = (bus_addr_t)rman_get_start(sc->res); in al_msix_attach()
154 /* Register this device to handle MSI interrupts */ in al_msix_attach()
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| /freebsd/sys/contrib/dev/athk/ath11k/ |
| H A D | pci.c | 1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <linux/msi.h>
50 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); in ath11k_pci_bus_wake_up()
57 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); in ath11k_pci_bus_release()
62 if (!ab->hw_params.static_window_map) in ath11k_pci_get_window_start()
78 struct ath11k_base *ab = ab_pci->ab; in ath11k_pci_select_window()
82 lockdep_assert_held(&ab_pci->window_lock); in ath11k_pci_select_window()
84 if (window != ab_pci->register_window) { in ath11k_pci_select_window()
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| /freebsd/sys/dev/nvme/ |
| H A D | nvme_pci.c | 1 /*-
2 * Copyright (C) 2012-2016 Intel Corporation
81 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" },
83 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" },
102 if (devid != ep->devid) in nvme_match()
105 if (!ep->match_subdevice) in nvme_match()
108 if (subdevice == ep->subdevice) in nvme_match()
126 while (ep->devid) { in nvme_pci_probe()
131 if (ep->devid) in nvme_pci_probe()
132 ctrlr->quirks = ep->quirks; in nvme_pci_probe()
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