| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | mstar,msc313-mpll.yaml | 4 $id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#
7 title: MStar/Sigmastar MSC313 MPLL
13 The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
20 const: mstar,msc313-mpll
41 mpll@206000 {
42 compatible = "mstar,msc313-mpll";
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| H A D | imx7ulp-clock.txt | 34 "rosc", "sosc", "sirc", "firc", "upll", "mpll".
52 "mpll", "firc_bus_clk", "rosc", "spll_bus_clk";
67 <&firc>, <&upll>, <&mpll>;
69 "firc", "upll", "mpll";
90 "upll", "sosc_bus_clk", "mpll",
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| H A D | mstar,msc313-cpupll.yaml | 39 #include <dt-bindings/clock/mstar-msc313-mpll.h>
44 clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
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| H A D | sophgo,sg2042-clkgen.yaml | 28 - const: mpll
56 clock-names = "mpll",
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| H A D | mvebu-core-clock.txt | 38 3 = mpll (MPLL Clock)
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| H A D | imx31-clock.yaml | 22 mpll 3
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| H A D | imx35-clock.yaml | 20 mpll 1
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| H A D | imx25-clock.yaml | 21 mpll 2
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| H A D | sprd,sc9863a-clk.yaml | 27 - sprd,sc9863a-mpll
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| /freebsd/sys/contrib/device-tree/src/arm/sigmastar/ |
| H A D | mstar-v7.dtsi | 9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
153 mpll: mpll@206000 { label
154 compatible = "mstar,msc313-mpll";
164 clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
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| /freebsd/sys/contrib/device-tree/src/arm/qcom/ |
| H A D | qcom-ipq8064-v2.0.dtsi | 62 qcom,mpll = <5>;
68 qcom,mpll = <5>;
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | qcom,ipq806x-usb-phy-ss.yaml | 49 qcom,mpll:
51 description: Override value for mpll.
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| /freebsd/sys/contrib/device-tree/src/arm64/sprd/ |
| H A D | sharkl3.dtsi | 91 mpll: mpll@0 { label
92 compatible = "sprd,sc9863a-mpll";
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | samsung,exynos4212-fimc-is.yaml | 55 - const: mpll
183 "mcuispdiv1", "mpll", "aclk200",
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| H A D | exynos4-fimc-is.txt | 19 "mpll", "sysreg", "isp", "drc", "fd", "mcuisp", "gicisp",
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| H A D | samsung,fimc.yaml | 233 "mcuispdiv1", "mpll", "aclk200",
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | mstar-msc313-mpll.h | 3 * Output definitions for the MStar/SigmaStar MPLL
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| H A D | s3c2410.h | 22 #define MPLL 2 macro
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| H A D | s3c2412.h | 22 #define MPLL 2 macro
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| H A D | s3c2443.h | 26 #define MPLL 7 macro
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | mdio-mux-meson-g12a.txt | 14 * "clkin1" : SoC 50MHz MPLL
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| H A D | amlogic,g12a-mdio-mux.yaml | 31 - description: SoC 50MHz MPLL
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| /freebsd/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos5422-odroid-core.dtsi | 45 /* derived from 532MHz MPLL */
137 /* derived from 532MHz MPLL */
185 /* derived from 532MHz MPLL */
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| H A D | exynos4x12.dtsi | 514 "mcuispdiv1", "mpll", "aclk200",
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| /freebsd/sys/dev/hdmi/ |
| H A D | dwc_hdmi.c | 303 * PLL/MPLL config, see section 24.7.22 in TRM in dwc_hdmi_phy_configure()
321 * Values described in TRM section 34.9.2 PLL/MPLL Generic in dwc_hdmi_phy_configure()
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