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Searched full:mpidr_el1 (Results 1 – 17 of 17) sorted by relevance

/linux/arch/arm64/kernel/
H A Dsleep.S10 * Implementation of MPIDR_EL1 hash algorithm through shifting
18 * @mpidr: register containing MPIDR_EL1 value
79 mrs x7, mpidr_el1
120 mrs x1, mpidr_el1
H A Dsetup.c137 * An index can be created from the MPIDR_EL1 by isolating the in smp_build_mpidr_hash()
141 * the MPIDR_EL1 through shifting and ORing. It is a collision free in smp_build_mpidr_hash()
144 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. in smp_build_mpidr_hash()
H A Dhead.S353 mrs x2, mpidr_el1
H A Dcpufeature.c3668 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml69 and matches the MPIDR_EL1 register affinity bits.
74 bits [39:32] of MPIDR_EL1.
77 bits [23:0] of MPIDR_EL1.
82 of MPIDR_EL1.
/linux/tools/arch/arm64/include/asm/
H A Dcputype.h294 return read_cpuid(MPIDR_EL1); in read_cpuid_mpidr()
H A Dsysreg.h626 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
/linux/arch/arm64/include/asm/
H A Del2_setup.h141 mrs x1, mpidr_el1
H A Dkvm_emulate.h447 return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; in kvm_vcpu_get_mpidr_aff()
H A Dsysreg.h995 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
/linux/arch/arm64/kvm/hyp/include/hyp/
H A Dsysreg-sr.h157 write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); in __sysreg_restore_el1_state()
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_sllc_pmu.c293 * while SCCL_ID is from MPIDR_EL1 by CPU. in hisi_sllc_pmu_init_data()
H A Dhisi_uncore_pmu.c405 * determined from the MPIDR_EL1, but the encoding varies by CPU:
/linux/Documentation/arch/arm64/
H A Dcpu-feature-registers.rst407 get_cpu_ftr(MPIDR_EL1);
/linux/tools/testing/selftests/kvm/aarch64/
H A Dget-reg-list.c411 ARM64_SYS_REG(3, 0, 0, 0, 5), /* MPIDR_EL1 */
/linux/arch/arm64/tools/
H A Dsysreg2362 Field 26 MPIDR_EL1
/linux/arch/arm64/kvm/
H A Demulate-nested.c1254 SR_FGT(SYS_MPIDR_EL1, HFGxTR, MPIDR_EL1, 1),