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/linux/arch/arm/kernel/
H A Dsleep.S11 * Implementation of MPIDR hash algorithm through shifting
18 * @mpidr: register containing MPIDR value
19 * @mask: register containing MPIDR mask
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
27 * u32 mpidr_masked = mpidr & mask;
33 * Input registers: rs0, rs1, rs2, mpidr, mask
36 (eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
39 and \mpidr, \mpidr, \mask @ mask out MPIDR bits
40 and \dst, \mpidr, #0xff @ mask=aff0
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H A Dtopology.c188 unsigned int mpidr; in store_cpu_topology() local
193 mpidr = read_cpuid_mpidr(); in store_cpu_topology()
196 if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) { in store_cpu_topology()
202 if (mpidr & MPIDR_MT_BITMASK) { in store_cpu_topology()
204 cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in store_cpu_topology()
205 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); in store_cpu_topology()
206 cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 2); in store_cpu_topology()
210 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in store_cpu_topology()
211 cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); in store_cpu_topology()
226 pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n", in store_cpu_topology()
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H A Ddevtree.c60 * and builds the cpu logical map array containing MPIDR values related to
70 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must in arm_dt_init_cpu_maps()
76 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; in arm_dt_init_cpu_maps() local
92 * defines the MPIDR[23:0]. in arm_dt_init_cpu_maps()
104 * to avoid matching valid MPIDR[23:0] values. in arm_dt_init_cpu_maps()
114 * Build a stashed array of MPIDR values. Numbering scheme in arm_dt_init_cpu_maps()
118 * boot CPU MPIDR is detected, this is recorded so that the in arm_dt_init_cpu_maps()
122 if (hwid == mpidr) { in arm_dt_init_cpu_maps()
151 pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n"); in arm_dt_init_cpu_maps()
/linux/arch/arm64/kernel/
H A Dsleep.S18 * @mpidr: register containing MPIDR_EL1 value
19 * @mask: register containing MPIDR mask
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
27 * u64 mpidr_masked = mpidr & mask;
34 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
37 (eg: a macro instance with mpidr = x1 and dst = x1 is invalid)
39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
40 and \mpidr, \mpidr, \mask // mask out MPIDR bits
41 and \dst, \mpidr, #0xff // mask=aff0
43 and \mask, \mpidr, #0xff00 // mask = aff1
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H A Dsetup.c91 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; in smp_setup_processor_id() local
92 set_cpu_logical_map(0, mpidr); in smp_setup_processor_id()
95 (unsigned long)mpidr, read_cpuid_id()); in smp_setup_processor_id()
107 * MPIDR value. Resulting algorithm is a collision
154 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", in smp_build_mpidr_hash()
166 pr_warn("Large number of MPIDR hash buckets detected\n"); in smp_build_mpidr_hash()
/linux/arch/arm/mach-milbeaut/
H A Dplatsmp.c25 unsigned int mpidr, cpu, cluster; in m10v_boot_secondary() local
30 mpidr = cpu_logical_map(l_cpu); in m10v_boot_secondary()
31 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in m10v_boot_secondary()
32 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in m10v_boot_secondary()
48 unsigned int mpidr, cpu, cluster; in m10v_smp_init() local
59 mpidr = read_cpuid_mpidr(); in m10v_smp_init()
60 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in m10v_smp_init()
61 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in m10v_smp_init()
78 unsigned int mpidr, cpu; in m10v_cpu_kill() local
80 mpidr = cpu_logical_map(l_cpu); in m10v_cpu_kill()
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/linux/arch/arm/common/
H A Dmcpm_platsmp.c22 unsigned int mpidr; in cpu_to_pcpu() local
24 mpidr = cpu_logical_map(cpu); in cpu_to_pcpu()
25 *pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in cpu_to_pcpu()
26 *pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in cpu_to_pcpu()
73 unsigned int mpidr, pcpu, pcluster; in mcpm_cpu_die() local
74 mpidr = read_cpuid_mpidr(); in mcpm_cpu_die()
75 pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_die()
76 pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in mcpm_cpu_die()
H A Dmcpm_entry.c241 unsigned int mpidr, cpu, cluster; in mcpm_cpu_power_down() local
245 mpidr = read_cpuid_mpidr(); in mcpm_cpu_power_down()
246 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_power_down()
247 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in mcpm_cpu_power_down()
330 unsigned int mpidr = read_cpuid_mpidr(); in mcpm_cpu_suspend() local
331 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_suspend()
332 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in mcpm_cpu_suspend()
342 unsigned int mpidr, cpu, cluster; in mcpm_cpu_powered_up() local
349 mpidr = read_cpuid_mpidr(); in mcpm_cpu_powered_up()
350 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_powered_up()
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H A DbL_switcher.c46 * Use our own MPIDR accessors as the generic ones in asm/cputype.h have
124 unsigned int mpidr = read_mpidr(); in bL_switchpoint() local
125 unsigned int clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1); in bL_switchpoint()
149 unsigned int mpidr, this_cpu, that_cpu; in bL_switch_to() local
169 pr_debug("before switch: CPU %d MPIDR %#x -> %#x\n", in bL_switch_to()
236 mpidr = read_mpidr(); in bL_switch_to()
237 pr_debug("after switch: CPU %d MPIDR %#x\n", this_cpu, mpidr); in bL_switch_to()
238 BUG_ON(mpidr != ib_mpidr); in bL_switch_to()
515 int bL_switcher_get_logical_index(u32 mpidr) in bL_switcher_get_logical_index() argument
522 mpidr &= MPIDR_HWID_BITMASK; in bL_switcher_get_logical_index()
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/linux/arch/arm/mach-hisi/
H A Dplatmcpm.c100 unsigned int mpidr, cpu, cluster; in hip04_boot_secondary() local
104 mpidr = cpu_logical_map(l_cpu); in hip04_boot_secondary()
105 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in hip04_boot_secondary()
106 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in hip04_boot_secondary()
155 unsigned int mpidr, cpu, cluster; in hip04_cpu_die() local
158 mpidr = cpu_logical_map(l_cpu); in hip04_cpu_die()
159 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in hip04_cpu_die()
160 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in hip04_cpu_die()
193 unsigned int mpidr, cpu, cluster; in hip04_cpu_kill() local
196 mpidr = cpu_logical_map(l_cpu); in hip04_cpu_kill()
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/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst90 values: | mpidr | offset |
100 specified by the mpidr.
111 The mpidr field is used to specify which
112 redistributor is accessed. The mpidr is ignored for the distributor.
114 The mpidr encoding is based on the affinity information in the
115 architecture defined MPIDR, and the field is encoded as follows::
121 regardless of the mpidr used to access the register.
184 values: | mpidr | RES | instr |
186 The mpidr field encodes the CPU ID based on the affinity information in the
187 architecture defined MPIDR, and the field is encoded as follows::
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/linux/arch/arm64/include/asm/
H A Dsmp_plat.h30 * Retrieve logical cpu index corresponding to a given MPIDR.Aff*
31 * - mpidr: MPIDR.Aff* bits to be used for the look-up
35 static inline int get_logical_index(u64 mpidr) in get_logical_index() argument
39 if (cpu_logical_map(cpu) == mpidr) in get_logical_index()
/linux/drivers/bus/
H A Darm-cci.c117 u64 mpidr; member
132 static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr) in init_cpu_port() argument
135 port->mpidr = mpidr; in init_cpu_port()
143 static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr) in cpu_port_match() argument
145 return port->mpidr == (mpidr & MPIDR_HWID_BITMASK); in cpu_port_match()
254 * @mpidr: mpidr of the CPU whose CCI port should be disabled
265 int notrace cci_disable_port_by_cpu(u64 mpidr) in cci_disable_port_by_cpu() argument
271 if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) { in cci_disable_port_by_cpu()
302 " mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n" in cci_enable_port_for_self()
309 /* Loop over the cpu_port array looking for a matching MPIDR */ in cci_enable_port_for_self()
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/linux/arch/arm/include/asm/
H A Dsmp_plat.h75 * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
76 * - mpidr: MPIDR[23:0] to be used for the look-up
80 static inline int get_logical_index(u32 mpidr) in get_logical_index() argument
84 if (cpu_logical_map(cpu) == mpidr) in get_logical_index()
/linux/arch/arm64/kvm/hyp/nvhe/
H A Dpsci-relay.c78 static unsigned int find_cpu_id(u64 mpidr) in find_cpu_id() argument
83 if (mpidr & ~MPIDR_HWID_BITMASK) in find_cpu_id()
87 if (cpu_logical_map(i) == mpidr) in find_cpu_id()
109 DECLARE_REG(u64, mpidr, host_ctxt, 1); in psci_cpu_on()
119 * Find the logical CPU ID for the given MPIDR. The search set is in psci_cpu_on()
125 cpu_id = find_cpu_id(mpidr); in psci_cpu_on()
140 ret = psci_call(func_id, mpidr, in psci_cpu_on()
/linux/arch/arm/mach-sunxi/
H A Dmc_smp.c393 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_boot_secondary() local
395 mpidr = cpu_logical_map(l_cpu); in sunxi_mc_smp_boot_secondary()
396 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in sunxi_mc_smp_boot_secondary()
397 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in sunxi_mc_smp_boot_secondary()
445 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_cpu_die() local
448 mpidr = cpu_logical_map(l_cpu); in sunxi_mc_smp_cpu_die()
449 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in sunxi_mc_smp_cpu_die()
450 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in sunxi_mc_smp_cpu_die()
535 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_cpu_kill() local
540 mpidr = cpu_logical_map(l_cpu); in sunxi_mc_smp_cpu_kill()
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/linux/arch/arm/mach-shmobile/
H A Dheadsmp.S48 mrc p15, 0, r0, c0, c0, 5 @ r0 = MPIDR
93 * Per-CPU SMP boot function/argument selection code based on MPIDR
97 mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
103 add r5, r5, r2 @ array of per-cpu mpidr values
/linux/arch/arm/mach-exynos/
H A Dplatsmp.c51 u32 mpidr = cpu_logical_map(cpu); in platform_do_lowpower() local
52 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in platform_do_lowpower()
320 u32 mpidr = cpu_logical_map(cpu); in exynos_boot_secondary() local
321 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in exynos_boot_secondary()
425 u32 mpidr = cpu_logical_map(cpu); in exynos_cpu_die() local
426 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in exynos_cpu_die()
/linux/drivers/irqchip/
H A Dirq-gic-v3.c213 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) argument
776 u64 mpidr = cpu_logical_map(cpu); in gic_cpu_to_affinity() local
781 mpidr = (MPIDR_AFFINITY_LEVEL(mpidr, 1) | in gic_cpu_to_affinity()
782 (MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8)); in gic_cpu_to_affinity()
784 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | in gic_cpu_to_affinity()
785 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | in gic_cpu_to_affinity()
786 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | in gic_cpu_to_affinity()
787 MPIDR_AFFINITY_LEVEL(mpidr, 0)); in gic_cpu_to_affinity()
1050 unsigned long mpidr; in __gic_populate_rdist() local
1058 mpidr = gic_cpu_to_affinity(smp_processor_id()); in __gic_populate_rdist()
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/linux/arch/arm/mach-versatile/
H A Dspc.c98 * It corresponds to A15 processors MPIDR[15:8] bitfield
142 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
143 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
175 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
176 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
197 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
225 * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
226 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
H A Dtc2_pm.c202 unsigned int mpidr, cpu, cluster; in tc2_pm_init() local
242 mpidr = read_cpuid_mpidr(); in tc2_pm_init()
243 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in tc2_pm_init()
244 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in tc2_pm_init()
/linux/drivers/cpufreq/
H A Dtegra194-cpufreq.c107 static void tegra_get_cpu_mpidr(void *mpidr) in tegra_get_cpu_mpidr() argument
109 *((u64 *)mpidr) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; in tegra_get_cpu_mpidr()
114 u64 mpidr; in tegra234_get_cpu_cluster_id() local
116 smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); in tegra234_get_cpu_cluster_id()
119 *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 1); in tegra234_get_cpu_cluster_id()
121 *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 2); in tegra234_get_cpu_cluster_id()
209 u64 mpidr; in tegra194_get_cpu_cluster_id() local
211 smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); in tegra194_get_cpu_cluster_id()
214 *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 0); in tegra194_get_cpu_cluster_id()
216 *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1); in tegra194_get_cpu_cluster_id()
/linux/include/ras/
H A Dras_event.h178 __field(u64, mpidr)
191 __entry->mpidr = proc->mpidr;
193 __entry->mpidr = 0ULL;
204 TP_printk("affinity level: %d; MPIDR: %016llx; MIDR: %016llx; "
206 __entry->affinity, __entry->mpidr, __entry->midr,
/linux/include/linux/
H A Darm-cci.h26 extern int cci_disable_port_by_cpu(u64 mpidr);
34 static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; } in cci_disable_port_by_cpu() argument
/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c205 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len); in vgic_mmio_read_irouter()
231 irq->mpidr = val & GENMASK(23, 0); in vgic_mmio_write_irouter()
232 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr); in vgic_mmio_write_irouter()
322 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu); in vgic_mmio_read_v3r_typer() local
326 value = (u64)(mpidr & GENMASK(23, 0)) << 32; in vgic_mmio_read_v3r_typer()
1013 * The ICC_SGI* registers encode the affinity differently from the MPIDR,
1074 u64 mpidr; in vgic_v3_dispatch_sgi() local
1094 mpidr = SGI_AFFINITY_LEVEL(reg, 3); in vgic_v3_dispatch_sgi()
1095 mpidr |= SGI_AFFINITY_LEVEL(reg, 2); in vgic_v3_dispatch_sgi()
1096 mpidr |= SGI_AFFINITY_LEVEL(reg, 1); in vgic_v3_dispatch_sgi()
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