Home
last modified time | relevance | path

Searched full:mmio (Results 1 – 25 of 1485) sorted by relevance

12345678910>>...60

/linux/sound/pci/au88x0/
H A Dau88x0_xtalk.c248 hwwrite(vortex->mmio, 0x24200 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetLeftEQ()
249 hwwrite(vortex->mmio, 0x24204 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetLeftEQ()
250 hwwrite(vortex->mmio, 0x24208 + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetLeftEQ()
251 hwwrite(vortex->mmio, 0x2420c + i * 0x24, coefs[i][3]); in vortex_XtalkHw_SetLeftEQ()
252 hwwrite(vortex->mmio, 0x24210 + i * 0x24, coefs[i][4]); in vortex_XtalkHw_SetLeftEQ()
254 hwwrite(vortex->mmio, 0x24538, arg_0 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
255 hwwrite(vortex->mmio, 0x2453C, arg_4 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
265 hwwrite(vortex->mmio, 0x242b4 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetRightEQ()
266 hwwrite(vortex->mmio, 0x242b8 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetRightEQ()
267 hwwrite(vortex->mmio, 0x242bc + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetRightEQ()
[all …]
H A Dau88x0_core.c79 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_en_sr()
80 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); in vortex_mixer_en_sr()
84 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_dis_sr()
85 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel)); in vortex_mixer_dis_sr()
93 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
95 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
102 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
114 a = hwread(vortex->mmio,
139 a = hwread(vortex->mmio,
143 hwwrite(vortex->mmio,
[all …]
H A Dau88x0_eq.c41 hwwrite(vortex->mmio, 0x2b3c4, gain); in vortex_EqHw_SetTimeConsts()
42 hwwrite(vortex->mmio, 0x2b3c8, level); in vortex_EqHw_SetTimeConsts()
60 hwwrite(vortex->mmio, 0x2b000 + n * 0x30, coefs[i + 0]); in vortex_EqHw_SetLeftCoefs()
61 hwwrite(vortex->mmio, 0x2b004 + n * 0x30, coefs[i + 1]); in vortex_EqHw_SetLeftCoefs()
64 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, coefs[i + 2]); in vortex_EqHw_SetLeftCoefs()
65 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, coefs[i + 3]); in vortex_EqHw_SetLeftCoefs()
66 hwwrite(vortex->mmio, 0x2b010 + n * 0x30, coefs[i + 4]); in vortex_EqHw_SetLeftCoefs()
68 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, sign_invert(coefs[2 + i])); in vortex_EqHw_SetLeftCoefs()
69 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, sign_invert(coefs[3 + i])); in vortex_EqHw_SetLeftCoefs()
70 hwwrite(vortex->mmio, 0x2b010 + n * 0x30, sign_invert(coefs[4 + i])); in vortex_EqHw_SetLeftCoefs()
[all …]
H A Dau88x0_synth.c32 //temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2)); in vortex_wt_setstereo()
33 temp = hwread(vortex->mmio, WT_STEREO(wt)); in vortex_wt_setstereo()
35 //hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp); in vortex_wt_setstereo()
36 hwwrite(vortex->mmio, WT_STEREO(wt), temp); in vortex_wt_setstereo()
45 temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0)); in vortex_wt_setdsout()
50 hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp); in vortex_wt_setdsout()
70 hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000); in vortex_wt_allocroute()
71 //hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff); in vortex_wt_allocroute()
73 hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000); in vortex_wt_allocroute()
74 //hwwrite(vortex->mmio, WT_GMODE(1), 0xffffffff); in vortex_wt_allocroute()
[all …]
H A Dau88x0_mpu401.c16 /* Check for mpu401 mmio support. */
42 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) | in snd_vortex_midi()
44 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
48 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) & in snd_vortex_midi()
50 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
54 temp = hwread(vortex->mmio, VORTEX_CTRL2) & 0xffff00cf; in snd_vortex_midi()
56 hwwrite(vortex->mmio, VORTEX_CTRL2, temp); in snd_vortex_midi()
57 hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_RESET); in snd_vortex_midi()
60 temp = hwread(vortex->mmio, VORTEX_MIDI_DATA); in snd_vortex_midi()
66 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, in snd_vortex_midi()
[all …]
H A Dau88x0_a3d.c25 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
27 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
29 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
31 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
51 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
54 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
57 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
66 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
69 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
72 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810_main.c162 * @mmio: address of register space
168 static void i810_screen_off(u8 __iomem *mmio, u8 mode) in i810_screen_off() argument
173 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
174 val = i810_readb(SR_DATA, mmio); in i810_screen_off()
178 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); in i810_screen_off()
179 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
180 i810_writeb(SR_DATA, mmio, val); in i810_screen_off()
185 * @mmio: address of register space
192 static void i810_dram_off(u8 __iomem *mmio, u8 mode) in i810_dram_off() argument
196 val = i810_readb(DRAMCH, mmio); in i810_dram_off()
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-ufs.c41 void __iomem *mmio; member
62 void __iomem *mmio = phy->mmio; in ufs_mtk_phy_set_active() local
65 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); in ufs_mtk_phy_set_active()
66 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); in ufs_mtk_phy_set_active()
69 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_active()
70 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_active()
73 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_active()
74 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_active()
77 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_active()
78 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_active()
[all …]
/linux/drivers/net/ethernet/amd/
H A Damd8111e.c101 void __iomem *mmio = lp->mmio; in amd8111e_read_phy() local
105 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
107 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
110 ((reg & 0x1f) << 16), mmio + PHY_ACCESS); in amd8111e_read_phy()
112 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
131 void __iomem *mmio = lp->mmio; in amd8111e_write_phy() local
134 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
136 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
139 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); in amd8111e_write_phy()
142 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_irq.c33 static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg) in assert_iir_is_zero() argument
35 u32 val = xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
40 drm_WARN(&gt_to_xe(mmio)->drm, 1, in assert_iir_is_zero()
43 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
44 xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
45 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
46 xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
55 struct xe_gt *mmio = tile->primary_gt; in unmask_and_enable() local
61 assert_iir_is_zero(mmio, IIR(irqregs)); in unmask_and_enable()
63 xe_mmio_write32(mmio, IER(irqregs), bits); in unmask_and_enable()
[all …]
/linux/drivers/comedi/drivers/
H A Dni_pcidio.c311 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_request_di_mite_channel()
327 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_release_di_mite_channel()
393 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS); in nidio_interrupt()
394 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
408 dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL); in nidio_interrupt()
420 writeb(0x00, dev->mmio + in nidio_interrupt()
425 auxdata = readl(dev->mmio + GROUP_1_FIFO); in nidio_interrupt()
427 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
432 writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR); in nidio_interrupt()
435 writeb(0x00, dev->mmio + OP_MODE); in nidio_interrupt()
[all …]
/linux/drivers/ata/
H A Dsata_sx4.c419 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_dma_prep() local
428 mmio += PDC_CHIP0_OFS; in pdc20621_dma_prep()
458 /* copy three S/G tables and two packets to DIMM MMIO window */ in pdc20621_dma_prep()
466 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_dma_prep()
468 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_dma_prep()
470 ata_port_dbg(ap, "ata pkt buf ofs %u, prd size %u, mmio copied\n", in pdc20621_dma_prep()
478 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_nodata_prep() local
484 mmio += PDC_CHIP0_OFS; in pdc20621_nodata_prep()
495 /* copy three S/G tables and two packets to DIMM MMIO window */ in pdc20621_nodata_prep()
500 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_nodata_prep()
[all …]
H A Dahci_imx.c83 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) in imx_phy_crbit_assert() argument
90 crval = readl(mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
95 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
99 srval = readl(mmio + IMX_P0PHYSR); in imx_phy_crbit_assert()
108 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) in imx_phy_reg_addressing() argument
114 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_addressing()
117 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); in imx_phy_reg_addressing()
122 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); in imx_phy_reg_addressing()
129 static int imx_phy_reg_write(u16 val, void __iomem *mmio) in imx_phy_reg_write() argument
135 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_write()
[all …]
/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c214 struct engine_mmio *mmio; in restore_context_mmio_for_inhibit() local
231 for (mmio = gvt->engine_mmio_list.mmio; in restore_context_mmio_for_inhibit()
232 i915_mmio_reg_valid(mmio->reg); mmio++) { in restore_context_mmio_for_inhibit()
233 if (mmio->id != ring_id || !mmio->in_context) in restore_context_mmio_for_inhibit()
236 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
237 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); in restore_context_mmio_for_inhibit()
307 * Use lri command to initialize the mmio which is in context state image for
308 * inhibit context, it contains tracked engine mmio, render_mocs and
480 /* Switch ring mmio values (context). */
487 struct engine_mmio *mmio; in switch_mmio() local
[all …]
/linux/sound/soc/au1x/
H A Dpsc.h13 void __iomem *mmio; member
26 #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
27 #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
28 #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
29 #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
30 #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
31 #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
32 #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
33 #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
34 #define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmmio.c14 val = readl(dev->mmio.regs + offset); in mt76_mmio_rr()
23 writel(val, dev->mmio.regs + offset); in mt76_mmio_wr()
36 __iowrite32_copy(dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4)); in mt76_mmio_write_copy()
42 __ioread32_copy(data, dev->mmio.regs + offset, DIV_ROUND_UP(len, 4)); in mt76_mmio_read_copy()
74 spin_lock_irqsave(&dev->mmio.irq_lock, flags); in mt76_set_irq_mask()
75 dev->mmio.irqmask &= ~clear; in mt76_set_irq_mask()
76 dev->mmio.irqmask |= set; in mt76_set_irq_mask()
78 if (mtk_wed_device_active(&dev->mmio.wed)) in mt76_set_irq_mask()
79 mtk_wed_device_irq_set_mask(&dev->mmio.wed, in mt76_set_irq_mask()
80 dev->mmio.irqmask); in mt76_set_irq_mask()
[all …]
/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_mmio.h52 /* mmio scratchpad info */
68 * struct iosm_mmio - MMIO region mapped to the doorbell scratchpad.
69 * @base: Base address of MMIO region
94 * ipc_mmio_init - Allocate mmio instance data
95 * @mmio_addr: Mapped AP base address of the MMIO area.
98 * Returns: address of mmio instance data or NULL if fails.
106 * @ipc_mmio: Pointer to mmio instance
115 * MMIO instance to share it with CP during
117 * @ipc_mmio: Pointer to mmio instance
125 * @ipc_mmio: Pointer to mmio instance
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-ipq806x-sata.c19 void __iomem *mmio; member
59 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
61 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
63 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & in qcom_ipq806x_sata_phy_init()
68 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); in qcom_ipq806x_sata_phy_init()
70 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & in qcom_ipq806x_sata_phy_init()
77 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); in qcom_ipq806x_sata_phy_init()
79 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & in qcom_ipq806x_sata_phy_init()
82 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); in qcom_ipq806x_sata_phy_init()
85 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
[all …]
/linux/sound/soc/xilinx/
H A Dxlnx_formatter_pcm.c79 void __iomem *mmio; member
92 * @mmio: base address offset
99 void __iomem *mmio; member
287 reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS; in xlnx_mm2s_irq_handler()
306 reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS; in xlnx_s2mm_irq_handler()
354 stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET; in xlnx_formatter_pcm_open()
363 stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET; in xlnx_formatter_pcm_open()
367 val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG); in xlnx_formatter_pcm_open()
412 val = readl(stream_data->mmio + XLNX_AUD_CTRL); in xlnx_formatter_pcm_open()
414 writel(val, stream_data->mmio + XLNX_AUD_CTRL); in xlnx_formatter_pcm_open()
[all …]
/linux/tools/testing/selftests/kvm/
H A Dcoalesced_io_test.c19 uint64_t *mmio; member
53 WRITE_ONCE(*io->mmio, io->mmio_gpa + i); in guest_code()
60 WRITE_ONCE(*io->mmio, io->mmio_gpa + i); in guest_code()
64 WRITE_ONCE(*io->mmio, io->mmio_gpa + i); in guest_code()
88 * data_offset is garbage, e.g. an MMIO gpa. in vcpu_run_and_verify_io_exit()
95 TEST_ASSERT((!want_pio && (run->exit_reason == KVM_EXIT_MMIO && run->mmio.is_write && in vcpu_run_and_verify_io_exit()
96 run->mmio.phys_addr == io->mmio_gpa && run->mmio.len == 8 && in vcpu_run_and_verify_io_exit()
97 *(uint64_t *)run->mmio.data == io->mmio_gpa + io->ring_size - 1)) || in vcpu_run_and_verify_io_exit()
102 "(MMIO addr = 0x%llx, write = %u, len = %u, data = %lx)\n " in vcpu_run_and_verify_io_exit()
104 ring_start, want_pio ? 4 : 8, want_pio ? "PIO" : "MMIO", in vcpu_run_and_verify_io_exit()
[all …]
/linux/arch/loongarch/kvm/
H A Dexit.c356 run->mmio.phys_addr = vcpu->arch.badv; in kvm_emu_mmio_read()
368 run->mmio.len = 4; in kvm_emu_mmio_read()
371 run->mmio.len = 8; in kvm_emu_mmio_read()
383 run->mmio.len = 1; in kvm_emu_mmio_read()
387 run->mmio.len = 1; in kvm_emu_mmio_read()
390 run->mmio.len = 2; in kvm_emu_mmio_read()
394 run->mmio.len = 2; in kvm_emu_mmio_read()
397 run->mmio.len = 4; in kvm_emu_mmio_read()
401 run->mmio.len = 4; in kvm_emu_mmio_read()
404 run->mmio.len = 8; in kvm_emu_mmio_read()
[all …]
/linux/drivers/watchdog/
H A Dvia_wdt.c25 #define VIA_WDT_MMIO_BASE 0xe8 /* MMIO region base address */
30 #define VIA_WDT_CONF_MMIO 0x02 /* 1: enable watchdog MMIO */
33 * The MMIO region contains the watchdog control register and the
36 #define VIA_WDT_MMIO_LEN 8 /* MMIO region length in bytes */
37 #define VIA_WDT_CTL 0 /* MMIO addr+0: state/control reg. */
38 #define VIA_WDT_COUNT 4 /* MMIO addr+4: timer counter reg. */
69 static unsigned int mmio; variable
170 * Allocate a MMIO region which contains watchdog control register in wdt_probe()
177 dev_err(&pdev->dev, "MMIO allocation failed\n"); in wdt_probe()
186 pci_read_config_dword(pdev, VIA_WDT_MMIO_BASE, &mmio); in wdt_probe()
[all …]
/linux/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c121 writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS); in hibmc_plane_atomic_update()
128 priv->mmio + HIBMC_CRT_FB_WIDTH); in hibmc_plane_atomic_update()
131 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_plane_atomic_update()
135 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_plane_atomic_update()
165 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_dpms()
171 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_dpms()
183 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); in hibmc_crtc_atomic_enable()
205 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); in hibmc_crtc_atomic_disable()
259 val = readl(priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
261 writel(val, priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
[all …]
/linux/drivers/soundwire/
H A Damd_manager.c35 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); in amd_init_sdw_manager()
36 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, in amd_init_sdw_manager()
42 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); in amd_init_sdw_manager()
43 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, in amd_init_sdw_manager()
48 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); in amd_init_sdw_manager()
49 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val, in amd_init_sdw_manager()
57 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); in amd_init_sdw_manager()
58 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, in amd_init_sdw_manager()
66 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); in amd_enable_sdw_manager()
67 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, in amd_enable_sdw_manager()
[all …]
/linux/drivers/ntb/hw/amd/
H A Dntb_hw_amd.c125 void __iomem *mmio, *peer_mmio; in amd_ntb_mw_set_trans() local
142 mmio = ndev->self_mmio; in amd_ntb_mw_set_trans()
166 write64(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
189 writel(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
346 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_enable() local
350 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_enable()
362 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_disable() local
366 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_disable()
423 void __iomem *mmio = ndev->self_mmio; in amd_ntb_db_read() local
425 return (u64)readw(mmio + AMD_DBSTAT_OFFSET); in amd_ntb_db_read()
[all …]

12345678910>>...60