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/linux/drivers/input/serio/
H A Dhp_sdc_mlc.c2 * Access to HP-HIL MLC through HP System Device Controller.
45 #define PREFIX "HP SDC MLC: "
50 MODULE_DESCRIPTION("Glue for onboard HIL MLC in HP-PARISC machines");
65 hil_mlc *mlc = &hp_sdc_mlc; in hp_sdc_mlc_isr() local
67 write_lock(&mlc->lock); in hp_sdc_mlc_isr()
68 if (mlc->icount < 0) { in hp_sdc_mlc_isr()
70 up(&mlc->isem); in hp_sdc_mlc_isr()
73 idx = 15 - mlc->icount; in hp_sdc_mlc_isr()
75 mlc->ipacket[idx] |= data | HIL_ERR_INT; in hp_sdc_mlc_isr()
76 mlc->icount--; in hp_sdc_mlc_isr()
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H A DKconfig145 tristate "HIL MLC Support (needed for HIL input devices)"
/linux/include/linux/
H A Dhil_mlc.h91 typedef int (hilse_func) (hil_mlc *mlc, int arg);
105 typedef int (hil_mlc_cts) (hil_mlc *mlc);
106 typedef int (hil_mlc_out) (hil_mlc *mlc);
107 typedef int (hil_mlc_in) (hil_mlc *mlc, suseconds_t timeout);
117 hil_mlc *mlc; member
130 void *priv; /* Data specific to a particular type of MLC */
167 int hil_mlc_register(hil_mlc *mlc);
168 int hil_mlc_unregister(hil_mlc *mlc);
H A Dhp_sdc.h102 #define HP_SDC_STATUS_HILCMD 0x50 /* Command from HIL MLC */
103 #define HP_SDC_STATUS_HILDATA 0x60 /* Data from HIL MLC */
144 #define HP_SDC_IM_HIL 0x01 /* Mask the HIL MLC irq */
148 #define HP_SDC_CFG_NEW 0x20 /* Supports/uses HIL MLC */
158 #define HP_SDC_LPC_APE_IPF 0x01 /* HIL MLC APE/IPF (autopoll) set */
246 HIL MLC R0,R1 i8042 HIL watchdog */
248 /* Values used to (de)mangle input/output to/from the HIL MLC */
250 #define HP_SDC_HIL_CMD 0x50 /* Data from HIL MLC R1/8042 */
251 #define HP_SDC_HIL_R1MASK 0x0f /* Contents of HIL MLC R1 0:3 */
255 #define HP_SDC_HIL_ERR 0x81 /* HIL MLC R2 had a bit set */
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H A Dhil.h57 * implementing a software MLC to run HIL devices on a non-parisc machine.
101 /* The HIL MLC also has several error/status/control bits. We extend the
102 * "packet" to include these when direct access to the MLC is available,
105 * This way the device driver knows that the underlying MLC driver
109 HIL_ERR_OB = 0x00000800, /* MLC is busy sending an auto-poll,
/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-mlc.txt1 NXP LPC32xx SoC NAND MLC controller
4 - compatible: "nxp,lpc3220-mlc"
10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
26 mlc: flash@200a8000 {
27 compatible = "nxp,lpc3220-mlc";
/linux/arch/arm/mach-lpc32xx/
H A Dphy3250.c27 .bus_id = "nand-mlc",
28 .min_signal = 12, /* MLC NAND Flash */
67 OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
/linux/drivers/mtd/nand/raw/
H A Dlpc32xx_mlc.c3 * Driver for NAND MLC Controller in LPC32xx
38 * MLC NAND controller register offsets
235 /* Reset MLC controller */ in lpc32xx_nand_setup()
239 /* Get base clock for MLC block */ in lpc32xx_nand_setup()
248 /* Configure MLC Controller: Large Block, 5 Byte Address */ in lpc32xx_nand_setup()
540 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */ in lpc32xx_write_page_lowlevel()
554 /* Read whole page - necessary with MLC controller! */ in lpc32xx_read_oob()
562 /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */ in lpc32xx_write_oob()
566 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
587 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, "nand-mlc"); in lpc32xx_dma_setup()
[all …]
H A Dinternals.h79 /* MLC pairing schemes */
/linux/include/linux/mtd/
H A Dlpc32xx_mlc.h3 * Platform data for LPC32xx SoC MLC NAND controller
H A Donenand.h42 * device size ie when all blocks are considered MLC
/linux/drivers/video/fbdev/
H A Dimsttfb.c312 __u8 mlc[3]; /* Memory Loop Config 0x39 */ member
586 __u8 mlc, lckl_p; in set_imstt_regvals_tvp() local
594 mlc = init->mlc[0]; in set_imstt_regvals_tvp()
601 mlc = init->mlc[1]; in set_imstt_regvals_tvp()
608 mlc = init->mlc[2]; in set_imstt_regvals_tvp()
615 mlc = init->mlc[2]; in set_imstt_regvals_tvp()
645 par->cmap_regs[TVPIDATA] = mlc; eieio(); in set_imstt_regvals_tvp()
/linux/Documentation/devicetree/bindings/mfd/
H A Dhi6421.txt24 // supply for MLC NAND/ eMMC
/linux/include/uapi/mtd/
H A Dmtd-abi.h148 #define MTD_MLCNANDFLASH 8 /* MLC NAND (including TLC) */
154 #define MTD_SLC_ON_MLC_EMULATION 0x4000 /* Emulate SLC behavior on MLC NANDs */
/linux/drivers/mtd/ubi/
H A DKconfig27 However, in case of MLC NAND flashes which typically have eraseblock
/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dpartition.yaml51 on a partition attached to an MLC NAND thus making this partition
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Dpipeline.json441 …MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand l…
468 …MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ en…
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dpipeline.json450 …MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand l…
477 …MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ en…
/linux/Documentation/filesystems/
H A Dubifs.rst31 typically 100K-1G for SLC NAND and NOR flashes, and 1K-10K for MLC
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Dcache.json153 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
162 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
297 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c240 LPC32XX_CLK_DEFINE(MLC, "mlc", 0x0, LPC32XX_CLK_HCLK),
1355 LPC32XX_DEFINE_CLK(MLC, FLASHCLK_CTRL,
1566 /* Disable enabled by default clocks for NAND MLC and SLC */ in lpc32xx_clk_init()
/linux/Documentation/ABI/testing/
H A Dsysfs-class-mtd107 absent, ram, rom, nor, nand, mlc-nand, dataflash, ubi, unknown
/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-gr8-evb.dts239 /* MLC Support sucks for now */
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Dcache.json153 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
162 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
297 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
/linux/drivers/input/keyboard/
H A Dhil_kbd.c466 /* Get device info. MLC driver supplies devid/status/etc. */ in hil_dev_connect()

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