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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dsamsung,mipi-video-phy.yaml4 $id: http://devicetree.org/schemas/phy/samsung,mipi-video-phy.yaml#
7 title: Samsung S5P/Exynos SoC MIPI CSIS/DSIM DPHY
15 For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the
17 0 - MIPI CSIS 0,
18 1 - MIPI DSIM 0,
19 2 - MIPI CSIS 1,
20 3 - MIPI DSIM 1.
22 samsung,exynos5420-mipi-video-phy and samsung,exynos5433-mipi-video-phy
24 4 - MIPI CSIS 2.
29 - samsung,s5pv210-mipi-video-phy
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H A Dmediatek,dsi-phy.yaml8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
15 description: The MIPI DSI PHY supports up to 4-lane output.
25 - mediatek,mt7623-mipi-tx
26 - const: mediatek,mt2701-mipi-tx
29 - mediatek,mt6795-mipi-tx
30 - const: mediatek,mt8173-mipi-tx
33 - mediatek,mt8188-mipi-tx
34 - mediatek,mt8195-mipi-tx
35 - mediatek,mt8365-mipi-tx
36 - const: mediatek,mt8183-mipi
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H A Dallwinner,sun6i-a31-mipi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
22 - const: allwinner,sun50i-a64-mipi-dphy
23 - const: allwinner,sun6i-a31-mipi-dphy
25 - const: allwinner,sun20i-d1-mipi-dphy
26 - const: allwinner,sun50i-a100-mipi-dphy
51 - "rx" for receiving (e.g. when used with MIPI CSI-2);
52 - "tx" for transmitting (e.g. when used with MIPI DSI).
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H A Drockchip-mipi-dphy-rx0.yaml4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
24 - description: MIPI D-PHY RX0 cfg clock
53 * MIPI D-PHY RX0 use registers in "general register files", it
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
H A Dmixel,mipi-dsi-phy.yaml4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
59 const: fsl,imx8mq-mipi-dphy
73 const: fsl,imx8qxp-mipi-dphy
89 compatible = "fsl,imx8mq-mipi-dphy";
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra114-mipi.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
7 title: NVIDIA Tegra MIPI pad calibration controller
15 pattern: "^mipi@[0-9a-f]+$"
19 - nvidia,tegra114-mipi
20 - nvidia,tegra210-mipi
21 - nvidia,tegra186-mipi
32 - const: mipi-cal
37 "#nvidia,mipi-calibrate-cells":
38 description: The number of cells in a MIPI calibration specifier.
50 - "#nvidia,mipi-calibrate-cells"
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H A Dnvidia,tegra114-mipi.txt1 NVIDIA Tegra MIPI pad calibration controller
4 - compatible: "nvidia,tegra<chip>-mipi"
9 - mipi-cal
10 - #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
13 User nodes need to contain an nvidia,mipi-calibrate property that has a
19 mipi: mipi@700e3000 {
20 compatible = "nvidia,tegra114-mipi";
23 clock-names = "mipi-cal";
24 #nvidia,mipi-calibrate-cells = <1>;
35 nvidia,mipi-calibrate = <&mipi 0x060>;
/freebsd/sys/contrib/device-tree/Bindings/display/rockchip/
H A Drockchip,dw-mipi-dsi.yaml4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3128-mipi-dsi
19 - rockchip,rk3288-mipi-dsi
20 - rockchip,rk3399-mipi-dsi
21 - rockchip,rk3568-mipi-dsi
22 - rockchip,rv1126-mipi-dsi
23 - const: snps,dw-mipi-dsi
74 - $ref: /schemas/display/bridge/snps,dw-mipi-dsi.yaml#
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H A Ddw_mipi_dsi_rockchip.txt1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"
28 - power-domains: a phandle to mipi dsi power domain node.
37 mipi_dsi: mipi@ff960000 {
40 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dsamsung,mipi-dsim.yaml4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
7 title: Samsung MIPI DSIM bridge controller
15 Samsung MIPI DSIM bridge controller can be found it on Exynos
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
24 - samsung,exynos5410-mipi-dsi
25 - samsung,exynos5422-mipi-dsi
26 - samsung,exynos5433-mipi-dsi
27 - fsl,imx8mm-mipi-dsim
28 - fsl,imx8mp-mipi-dsim
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H A Dintel,keembay-dsi.yaml7 title: Intel Keem Bay mipi dsi controller
19 - description: MIPI registers range
23 - const: mipi
27 - description: MIPI DSI clock
28 - description: MIPI DSI econfig clock
29 - description: MIPI DSI config clock
43 description: MIPI DSI input port.
65 mipi-dsi@20900000 {
68 reg-names = "mipi";
H A Dlontium,lt9211.yaml41 Primary MIPI DSI port-1 for MIPI input or
47 Additional MIPI port-2 for MIPI input or LVDS port-2
54 Primary MIPI DSI port-1 for MIPI output or
60 Additional MIPI port-2 for MIPI output or LVDS port-2
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dnxp,imx-mipi-csi2.yaml4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
27 - fsl,imx7-mipi-csi2
28 - fsl,imx8mm-mipi-csi2
31 - fsl,imx8mp-mipi-csi2
32 - const: fsl,imx8mm-mipi-csi2
45 - description: The MIPI D-PHY clock
60 description: The MIPI D-PHY digital power supply
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H A Dnxp,imx7-mipi-csi2.yaml4 $id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
26 - fsl,imx7-mipi-csi2
27 - fsl,imx8mm-mipi-csi2
40 - description: The MIPI D-PHY clock
55 description: The MIPI D-PHY digital power supply
59 - description: MIPI D-PHY slave reset
83 Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
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H A Dallwinner,sun6i-a31-mipi-csi2.yaml4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
7 title: Allwinner A31 MIPI CSI-2
15 - const: allwinner,sun6i-a31-mipi-csi2
17 - const: allwinner,sun8i-v3s-mipi-csi2
18 - const: allwinner,sun6i-a31-mipi-csi2
38 description: MIPI D-PHY
53 description: Input port, connect to a MIPI CSI-2 sensor
101 compatible = "allwinner,sun8i-v3s-mipi-csi2",
102 "allwinner,sun6i-a31-mipi-csi2";
H A Dallwinner,sun8i-a83t-mipi-csi2.yaml4 $id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
7 title: Allwinner A83T MIPI CSI-2
14 const: allwinner,sun8i-a83t-mipi-csi2
26 - description: MIPI-specific Clock
33 - const: mipi
45 description: Input port, connect to a MIPI CSI-2 sensor
91 compatible = "allwinner,sun8i-a83t-mipi-csi2";
98 clock-names = "bus", "mod", "mipi", "misc";
H A Dimx7-mipi-csi2.txt1 Freescale i.MX7 Mipi CSI2
7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
12 - compatible : "fsl,imx7-mipi-csi2";
14 - interrupts : should contain MIPI CSIS interrupt;
25 provides power to MIPI CSIS core;
48 - data-lanes : (required) an array specifying active physical MIPI-CSI2
56 mipi_csi: mipi-csi@30750000 {
60 compatible = "fsl,imx7-mipi-csi2";
H A Dnxp,imx8mq-mipi-csi2.yaml4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
20 - fsl,imx8mq-mipi-csi2
50 fsl,mipi-phy-gpr:
53 for setting RX_ENABLE for the mipi receiver.
58 req_gpr is the gpr register offset of RX_ENABLE for the mipi phy.
116 - fsl,mipi-phy-gpr
128 compatible = "fsl,imx8mq-mipi-csi2";
145 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dallwinner,sun6i-a31-mipi-dsi.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
19 - allwinner,sun50i-a100-mipi-dsi
21 - const: allwinner,sun20i-d1-mipi-dsi
22 - const: allwinner,sun50i-a100-mipi-dsi
76 - allwinner,sun6i-a31-mipi-dsi
77 - allwinner,sun50i-a100-mipi-dsi
97 - allwinner,sun6i-a31-mipi-dsi
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/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos_dsim.txt1 Exynos MIPI DSI Master
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
19 - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
20 - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
23 according to DSI host bindings (see MIPI DSI bindings [1])
32 Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
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/freebsd/sys/contrib/device-tree/Bindings/i3c/
H A Dmipi-i3c-hci.yaml4 $id: http://devicetree.org/schemas/i3c/mipi-i3c-hci.yaml#
7 title: MIPI I3C HCI
16 MIPI I3C Host Controller Interface
18 The MIPI I3C HCI (Host Controller Interface) specification defines
19 a common software driver interface to support compliant MIPI I3C
27 https://www.mipi.org/specifications/i3c-hci
31 const: mipi-i3c-hci
47 compatible = "mipi-i3c-hci";
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dmipi-ccs.yaml5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
8 title: MIPI CCS, SMIA++ and SMIA compliant camera sensors
16 MIPI Alliance; see
17 <URL:https://www.mipi.org/specifications/camera-command-set>.
30 - const: mipi-ccs-1.1
31 - const: mipi-ccs
33 - const: mipi-ccs-1.0
34 - const: mipi-ccs
116 compatible = "mipi-ccs-1.0", "mipi-ccs";
/freebsd/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml7 title: Xilinx MIPI CSI-2 Receiver Subsystem
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
28 - xlnx,mipi-csi2-rx-subsystem-5.0
118 connects to MIPI CSI-2 source like sensor.
174 compatible = "xlnx,mipi-csi2-rx-subsystem-5.0";
196 /* MIPI CSI-2 Camera handle */
/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A Dfsl,imx8mp-media-blk-ctrl.yaml41 - const: mipi-dsi1
42 - const: mipi-csi1
45 - const: mipi-csi2
49 - const: mipi-dsi2
60 - description: The MIPI-PHY reference clock used by DSI
117 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
118 "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2";
/freebsd/sys/contrib/device-tree/Bindings/soundwire/
H A Dqcom,sdw.txt71 More info in MIPI Alliance SoundWire 1.0 Specifications.
80 More info in MIPI Alliance SoundWire 1.0 Specifications.
90 More info in MIPI Alliance SoundWire 1.0 Specifications.
98 More info in MIPI Alliance SoundWire 1.0 Specifications.
109 More info in MIPI Alliance SoundWire 1.0 Specifications.
119 More info in MIPI Alliance SoundWire 1.0 Specifications.
129 More info in MIPI Alliance SoundWire 1.0 Specifications.
140 More info in MIPI Alliance SoundWire 1.0 Specifications.
151 More info in MIPI Alliance SoundWire 1.0 Specifications.
163 More info in MIPI Alliance SoundWire 1.0 Specifications.
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