| /linux/Documentation/arch/arm/stm32/ |
| H A D | stm32-dma-mdma-chaining.rst | 4 STM32 DMA-MDMA chaining
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
33 **STM32 MDMA**
35 STM32 MDMA (Master DMA) is mainly used to manage direct data transfers between
38 interfaces for AHB peripherals, while the STM32 MDMA acts as a second level
39 DMA with better performance. As a AXI/AHB master, STM32 MDMA can take control
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
47 STM32 MDMA controllers.
52 counter is automatically reloaded. This allows the SW or the STM32 MDMA to
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| /linux/Documentation/devicetree/bindings/dma/stm32/ |
| H A D | st,stm32-mdma.yaml | 4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
7 title: STMicroelectronics STM32 MDMA Controller
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
12 DMA clients connected to the STM32 MDMA controller must use the format
14 a phandle to the MDMA controller plus the following five integer cells:
43 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
44 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
45 0x2: Each MDMA request triggers a repeated block transfer
46 0x3: Each MDMA request triggers a linked list transfer
48 if no HW ack signal is used by the MDMA client
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| /linux/drivers/dma/stm32/ |
| H A D | stm32-mdma.c | 8 * Driver for STM32 MDMA controller
35 #define STM32_MDMA_GISR0 0x0000 /* MDMA Int Status Reg 1 */
37 /* MDMA Channel x interrupt/status register */
46 /* MDMA Channel x interrupt flag clear register */
59 /* MDMA Channel x error status register */
68 /* MDMA Channel x control register */
89 /* MDMA Channel x transfer configuration register */
128 /* MDMA Channel x block number of data register */
139 /* MDMA Channel x source address register */
142 /* MDMA Channel x destination address register */
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| H A D | Kconfig | 32 Enable support for the on-chip MDMA controller on STMicroelectronics
35 and want to use MDMA say Y here.
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| H A D | Makefile | 4 obj-$(CONFIG_STM32_MDMA) += stm32-mdma.o
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| H A D | stm32-dma.c | 197 * struct stm32_dma_mdma_config - STM32 DMA MDMA configuration
198 * @stream_id: DMA request to trigger STM32 MDMA transfer
200 * used by STM32 MDMA to clear DMA Transfer Complete flag
404 /* Check if user is requesting DMA to trigger STM32 MDMA */ in stm32_dma_slave_config()
586 /* When DMA triggers STM32 MDMA, DMA Transfer Complete is managed by STM32 MDMA */ in stm32_dma_start_transfer()
1115 /* Activate Double Buffer Mode if DMA triggers STM32 MDMA and more than 1 sg */ in stm32_dma_prep_slave_sg()
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | ingenic,dma.yaml | 24 - ingenic,jz4760-mdma
27 - ingenic,jz4760b-mdma
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | st,stm32-spi.yaml | 82 - description: rxm2m MDMA channel
95 storage memory between DMA and MDMA engines.
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| /linux/drivers/rapidio/devices/ |
| H A D | tsi721.c | 115 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id); in tsi721_maint_dma()
127 bd_ptr = priv->mdma.bd_base; in tsi721_maint_dma()
155 priv->mdma.ch_id, ch_stat); in tsi721_maint_dma()
1458 priv->mdma.ch_id = TSI721_DMACH_MAINT; in tsi721_bdma_maint_init()
1468 priv->mdma.bd_num = bd_num; in tsi721_bdma_maint_init()
1469 priv->mdma.bd_phys = bd_phys; in tsi721_bdma_maint_init()
1470 priv->mdma.bd_base = bd_ptr; in tsi721_bdma_maint_init()
1487 priv->mdma.bd_base = NULL; in tsi721_bdma_maint_init()
1491 priv->mdma.sts_phys = sts_phys; in tsi721_bdma_maint_init()
1492 priv->mdma.sts_base = sts_ptr; in tsi721_bdma_maint_init()
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| H A D | tsi721.h | 889 struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */ member
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| /linux/drivers/ata/ |
| H A D | pata_pdc2027x.c | 85 { 0xdf, 0x5f }, /* MDMA mode 0 */
86 { 0x6b, 0x27 }, /* MDMA mode 1 */
87 { 0x69, 0x25 }, /* MDMA mode 2 */
357 /* Set the MDMA timing registers with value table for 133MHz */ in pdc2027x_set_dmamode()
360 ata_port_dbg(ap, "Set MDMA regs...\n"); in pdc2027x_set_dmamode()
369 ata_port_dbg(ap, "Set to MDMA mode[%u]\n", mdma_mode); in pdc2027x_set_dmamode()
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| H A D | pata_mpc52xx.c | 81 /* ATAPI-4 MDMA specs (in clocks) */
214 u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
215 u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
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| H A D | pata_macio.c | 65 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
111 * and MDMA, I think I've figured the format of the timing register,
167 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
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| H A D | pata_ep93xx.c | 99 /* MDMA Operation Register */
107 /* PIO/MDMA/UDMA Data Registers */
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| H A D | sata_sil.c | 365 /* value 2 indicates MDMA */ in sil_set_mode()
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| /linux/Documentation/arch/arm/ |
| H A D | index.rst | 63 stm32/stm32-dma-mdma-chaining
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| /linux/Documentation/devicetree/bindings/iommu/ |
| H A D | ti,omap-iommu.txt | 28 instance number should be 0 for DSP MDMA MMUs and 1 for
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| /linux/drivers/spi/ |
| H A D | spi-stm32.c | 337 * @mdma_rx: MDMA channel for RX transfer
1462 * stm32_spi_prepare_rx_dma_mdma_chaining - Prepare RX DMA and MDMA chaining
1467 * @rx_mdma_desc: pointer to the RX MDMA descriptor
1488 /* Configure MDMA RX channel */ in stm32_spi_prepare_rx_dma_mdma_chaining()
1537 /* Prepare MDMA slave_sg transfer MEM_TO_MEM (SRAM>DDR) */ in stm32_spi_prepare_rx_dma_mdma_chaining()
1603 if (ret) { /* RX DMA MDMA chaining not possible, fallback to DMA only */ in stm32_spi_transfer_one_dma()
1647 dev_err(spi->dev, "Rx MDMA submit failed\n"); in stm32_spi_transfer_one_dma()
1650 /* Enable Rx MDMA channel */ in stm32_spi_transfer_one_dma()
2436 dev_info(&pdev->dev, "SRAM pool: %zu KiB for RX DMA/MDMA chaining\n", in stm32_spi_probe()
2454 "failed to request rx mdma channel, DMA only\n"); in stm32_spi_probe()
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| /linux/include/dt-bindings/clock/ |
| H A D | stm32mp13-clks.h | 97 #define MDMA 69 macro
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| H A D | stm32mp1-clks.h | 113 #define MDMA 100 macro
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| /linux/drivers/clk/stm32/ |
| H A D | clk-stm32mp13.c | 887 static struct clk_stm32_gate mdma = { variable
889 .hw.init = CLK_HW_INIT("mdma", "ck_axi", &clk_stm32_gate_ops, 0),
1389 STM32_GATE_CFG(MDMA, mdma, SECF_NONE),
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| H A D | clk-stm32mp1.c | 1986 PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
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| /linux/drivers/clk/ingenic/ |
| H A D | jz4760-cgu.c | 325 "mdma", CGU_CLK_GATE,
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stm32h743.dtsi | 372 compatible = "st,stm32h7-mdma";
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| /linux/drivers/clk/samsung/ |
| H A D | clk-exynos4.c | 921 GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
969 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
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