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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mca.c89 if (!adev->mca.mp0.ras) in amdgpu_mca_mp0_ras_sw_init()
92 ras = adev->mca.mp0.ras; in amdgpu_mca_mp0_ras_sw_init()
96 dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n"); in amdgpu_mca_mp0_ras_sw_init()
100 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); in amdgpu_mca_mp0_ras_sw_init()
103 adev->mca.mp0.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp0_ras_sw_init()
113 if (!adev->mca.mp1.ras) in amdgpu_mca_mp1_ras_sw_init()
116 ras = adev->mca.mp1.ras; in amdgpu_mca_mp1_ras_sw_init()
120 dev_err(adev->dev, "Failed to register mca.mp1 ras block!\n"); in amdgpu_mca_mp1_ras_sw_init()
124 strcpy(ras->ras_block.ras_comm.name, "mca.mp1"); in amdgpu_mca_mp1_ras_sw_init()
127 adev->mca.mp1.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp1_ras_sw_init()
[all …]
H A Dumc_v6_7.c70 dev_info(adev->dev, "MCA STATUS 0x%llx, umc_reg_offset 0x%x\n", mc_umc_status, umc_reg_offset); in umc_v6_7_query_error_status_helper()
77 dev_info(adev->dev, "MCA IPID 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
84 dev_info(adev->dev, "MCA SYND 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
91 dev_info(adev->dev, "MCA MISC0 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
H A Damdgpu_umc.h81 /* three column bits and one row bit in MCA address flip
193 uint64_t pa, uint64_t *mca, enum amdgpu_memory_partition nps);
H A Damdgpu_ras_eeprom.h91 /* Number of records store mca address */
/linux/sound/soc/apple/
H A Dmca.c3 // Apple SoCs MCA driver
7 // The MCA peripheral is made up of a number of identical units called clusters.
181 struct mca_data *mca = snd_soc_dai_get_drvdata(dai); in mca_dai_to_cluster() local
186 int cluster_no = dai->id % mca->nclusters; in mca_dai_to_cluster()
188 return &mca->clusters[cluster_no]; in mca_dai_to_cluster()
261 struct mca_data *mca = cl->host; in mca_fe_enable_clocks() local
266 dev_err(mca->dev, in mca_fe_enable_clocks()
277 cl->pd_link = device_link_add(mca->dev, cl->pd_dev, in mca_fe_enable_clocks()
281 dev_err(mca->dev, in mca_fe_enable_clocks()
306 struct mca_data *mca in mca_fe_clocks_in_use() local
332 struct mca_data *mca = cl->host; mca_be_prepare() local
362 struct mca_data *mca = cl->host; mca_be_hw_free() local
505 struct mca_data *mca = cl->host; mca_fe_set_fmt() local
592 struct mca_data *mca = cl->host; mca_fe_hw_params() local
730 struct mca_data *mca = cl->host; mca_be_startup() local
780 struct mca_data *mca = cl->host; mca_be_shutdown() local
1009 apple_mca_release(struct mca_data * mca) apple_mca_release() argument
1034 struct mca_data *mca; apple_mca_probe() local
1187 struct mca_data *mca = platform_get_drvdata(pdev); apple_mca_remove() local
[all...]
H A DMakefile1 snd-soc-apple-mca-y := mca.o
3 obj-$(CONFIG_SND_SOC_APPLE_MCA) += snd-soc-apple-mca.o
H A DKconfig4 tristate "Apple Silicon MCA driver"
8 This option enables an ASoC platform driver for MCA peripherals found
/linux/drivers/infiniband/sw/rxe/
H A Drxe_mcast.c11 * struct rxe_mca ('mca'). An mcg is allocated each time a qp is
17 * mca is created. It holds a pointer to the qp and is added to a list
302 * __rxe_init_mca - initialize a new mca holding lock
305 * @mca: empty space for new mca
308 * and pass memory for new mca
313 struct rxe_mca *mca) in __rxe_init_mca() argument
334 mca->qp = qp; in __rxe_init_mca()
336 list_add_tail(&mca->qp_list, &mcg->qp_list); in __rxe_init_mca()
352 struct rxe_mca *mca, *tmp; in rxe_attach_mcg() local
357 list_for_each_entry(mca, &mcg->qp_list, qp_list) { in rxe_attach_mcg()
[all …]
H A Drxe_recv.c194 struct rxe_mca *mca; in rxe_rcv_mcast_pkt() local
217 list_for_each_entry(mca, &mcg->qp_list, qp_list) { in rxe_rcv_mcast_pkt()
218 qp = mca->qp; in rxe_rcv_mcast_pkt()
233 if (mca->qp_list.next != &mcg->qp_list) { in rxe_rcv_mcast_pkt()
/linux/arch/x86/include/asm/
H A Dmce.h20 #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
57 * McaX field if set indicates a given bank supports MCA extensions:
76 #define MCACOD 0xefff /* MCA Error Code */
115 /* AMD Scalable MCA */
262 /* Maximum number of MCA banks per CPU. */
302 /* Disable CMCI/polling for MCA bank claimed by firmware */
328 * Scalable MCA.
H A Dmpspec_def.h88 #define BUSTYPE_MCA "MCA" /* Obsolete */
171 * 4 2 CPU MCA 82489DX
174 * 7 2 CPU MCA+PCI
/linux/net/packet/
H A Ddiag.c40 struct nlattr *mca; in pdiag_put_mclist() local
43 mca = nla_nest_start_noflag(nlskb, PACKET_DIAG_MCLIST); in pdiag_put_mclist()
44 if (!mca) in pdiag_put_mclist()
54 nla_nest_cancel(nlskb, mca); in pdiag_put_mclist()
67 nla_nest_end(nlskb, mca); in pdiag_put_mclist()
/linux/arch/x86/kernel/cpu/mce/
H A Damd.c50 /* Scalable MCA: */
152 /* ZN Core (HWID=0xB0) MCA types */
163 /* Data Fabric MCA types */
169 /* Unified Memory Controller MCA type */
173 /* Parameter Block MCA type */
176 /* Platform Security Processor MCA type */
180 /* System Management Unit MCA type */
184 /* Microprocessor 5 Unit MCA type */
187 /* MPDMA MCA type */
190 /* Northbridge IO Unit MCA type */
[all …]
H A Dinternal.h207 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
208 * the register space for each MCA bank and also increases number of
209 * banks. Also, to accommodate the new banks and registers, the MCA
220 /* Pentium, family 5-style MCA */
223 /* Centaur Winchip C6-style MCA */
H A Dcore.c95 * MCA banks polled by the period polling timer for corrected events.
96 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
103 * MCA banks controlled through firmware first for corrected errors.
384 panic("MCA architectural violation!\n"); in ex_handler_msr_mce()
413 * RDMSR on MCA MSRs should not fault. If they do, this is very much an in mce_rdmsrq()
944 * The Instruction Fetch Unit is at MCA bank 1 for all affected systems.
1001 * Track which CPUs entered the MCA broadcast synchronization and which not in
2002 * These CPUs have MCA bank 8 which reports only one error type called in mce_zhaoxin_feature_init()
2299 "Ignoring request to disable invalid MCA bank %d.\n", in mce_disable_bank()
H A Dintel.c36 * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
39 * taking ownership of some of the shared MCA banks that were previously
/linux/include/uapi/misc/
H A Damd-apml.h49 * [0]...[3] mca msr func,
55 * Status code for MCA/MSR access
130 * - MCAMSR protocol to get MCA bank details for Function at thread level
/linux/arch/x86/xen/
H A Dtrace.c4 #include <xen/interface/xen-mca.h>
H A Dxen-head.S22 #include <xen/interface/xen-mca.h>
/linux/arch/m68k/
H A DKconfig.bus46 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
/linux/drivers/acpi/apei/
H A Dhest.c42 * structures for MCA.
43 * During HEST parsing, detected MCA error sources are cached from early
/linux/drivers/misc/amd-sbi/
H A Drmi-core.c189 /* MCA MSR protocol */
206 /* MCA MSR protocol for REV 0x10 is not supported*/ in rmi_mca_msr_read()
/linux/arch/x86/include/asm/xen/
H A Dhypercall.h55 #include <xen/interface/xen-mca.h>
410 return _hypercall1(int, mca, mc_op); in HYPERVISOR_mca()
/linux/Documentation/mm/
H A Dhwpoison.rst9 (``MCA recovery``). This requires the OS to declare a page "poisoned",
/linux/drivers/ras/amd/atl/
H A Dcore.c181 * and the set of systems with the Scalable MCA feature at this time. However, these

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