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/linux/drivers/memory/tegra/
H A Dmc.c22 #include "mc.h"
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
41 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
44 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
47 { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
50 { .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },
[all …]
H A Dtegra20.c14 #include <dt-bindings/memory/tegra20-mc.h>
16 #include "mc.h"
75 const struct tegra_mc *mc; member
279 static int tegra20_mc_hotreset_assert(struct tegra_mc *mc, in tegra20_mc_hotreset_assert() argument
285 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_assert()
287 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_assert()
288 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_assert()
290 spin_unlock_irqrestore(&mc->lock, flags); in tegra20_mc_hotreset_assert()
295 static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc, in tegra20_mc_hotreset_deassert() argument
301 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_deassert()
[all …]
H A DMakefile2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
10 tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
11 tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
12 tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186.o tegra234.o
[all …]
H A Dtegra186.c14 #include <soc/tegra/mc.h>
17 #include <dt-bindings/memory/tegra186-mc.h>
20 #include "mc.h"
26 static int tegra186_mc_probe(struct tegra_mc *mc) in tegra186_mc_probe() argument
28 struct platform_device *pdev = to_platform_device(mc->dev); in tegra186_mc_probe()
35 * From Tegra264, the SID region is not present in MC node and BROADCAST is first. in tegra186_mc_probe()
38 * the first entry mapped in mc probe as the BROADCAST region. This is done to avoid in tegra186_mc_probe()
43 mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast"); in tegra186_mc_probe()
45 mc->bcast_ch_regs = mc->regs; in tegra186_mc_probe()
47 if (IS_ERR(mc->bcast_ch_regs)) { in tegra186_mc_probe()
[all …]
/linux/sound/soc/
H A Dsoc-ops.c113 static int sdca_soc_q78_reg_to_ctl(struct soc_mixer_control *mc, unsigned int reg_val, in sdca_soc_q78_reg_to_ctl() argument
119 if (WARN_ON(!mc->shift)) in sdca_soc_q78_reg_to_ctl()
122 val = sign_extend32(val, mc->sign_bit); in sdca_soc_q78_reg_to_ctl()
123 val = (((val * 100) >> 8) / (int)mc->shift); in sdca_soc_q78_reg_to_ctl()
124 val -= mc->min; in sdca_soc_q78_reg_to_ctl()
129 static unsigned int sdca_soc_q78_ctl_to_reg(struct soc_mixer_control *mc, int val, in sdca_soc_q78_ctl_to_reg() argument
135 if (WARN_ON(!mc->shift)) in sdca_soc_q78_ctl_to_reg()
138 reg_val = val + mc->min; in sdca_soc_q78_ctl_to_reg()
139 ret_val = (int)((reg_val * mc->shift) << 8) / 100; in sdca_soc_q78_ctl_to_reg()
144 static int soc_mixer_reg_to_ctl(struct soc_mixer_control *mc, unsigned int reg_val, in soc_mixer_reg_to_ctl() argument
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/linux/drivers/gpio/
H A Dgpio-mc33880.c43 static int mc33880_write_config(struct mc33880 *mc) in mc33880_write_config() argument
45 return spi_write(mc->spi, &mc->port_config, sizeof(mc->port_config)); in mc33880_write_config()
49 static int __mc33880_set(struct mc33880 *mc, unsigned offset, int value) in __mc33880_set() argument
52 mc->port_config |= 1 << offset; in __mc33880_set()
54 mc->port_config &= ~(1 << offset); in __mc33880_set()
56 return mc33880_write_config(mc); in __mc33880_set()
62 struct mc33880 *mc = gpiochip_get_data(chip); in mc33880_set() local
65 mutex_lock(&mc->lock); in mc33880_set()
67 ret = __mc33880_set(mc, offset, value); in mc33880_set()
69 mutex_unlock(&mc->lock); in mc33880_set()
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/linux/drivers/dma/
H A Dmilbeaut-hdmac.c95 /* mc->vc.lock must be held by caller */
97 milbeaut_hdmac_next_desc(struct milbeaut_hdmac_chan *mc) in milbeaut_hdmac_next_desc() argument
101 vd = vchan_next_desc(&mc->vc); in milbeaut_hdmac_next_desc()
103 mc->md = NULL; in milbeaut_hdmac_next_desc()
109 mc->md = to_milbeaut_hdmac_desc(vd); in milbeaut_hdmac_next_desc()
111 return mc->md; in milbeaut_hdmac_next_desc()
114 /* mc->vc.lock must be held by caller */
115 static void milbeaut_chan_start(struct milbeaut_hdmac_chan *mc, in milbeaut_chan_start() argument
128 width = mc->cfg.dst_addr_width; in milbeaut_chan_start()
129 burst = mc->cfg.dst_maxburst; in milbeaut_chan_start()
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H A Duniphier-mdmac.c86 /* mc->vc.lock must be held by caller */
88 uniphier_mdmac_next_desc(struct uniphier_mdmac_chan *mc) in uniphier_mdmac_next_desc() argument
92 vd = vchan_next_desc(&mc->vc); in uniphier_mdmac_next_desc()
94 mc->md = NULL; in uniphier_mdmac_next_desc()
100 mc->md = to_uniphier_mdmac_desc(vd); in uniphier_mdmac_next_desc()
102 return mc->md; in uniphier_mdmac_next_desc()
105 /* mc->vc.lock must be held by caller */
106 static void uniphier_mdmac_handle(struct uniphier_mdmac_chan *mc, in uniphier_mdmac_handle() argument
109 struct uniphier_mdmac_device *mdev = mc->mdev; in uniphier_mdmac_handle()
130 writel(src_mode, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SRC_MODE); in uniphier_mdmac_handle()
[all …]
H A Dmilbeaut-xdmac.c92 /* mc->vc.lock must be held by caller */
94 milbeaut_xdmac_next_desc(struct milbeaut_xdmac_chan *mc) in milbeaut_xdmac_next_desc() argument
98 vd = vchan_next_desc(&mc->vc); in milbeaut_xdmac_next_desc()
100 mc->md = NULL; in milbeaut_xdmac_next_desc()
106 mc->md = to_milbeaut_xdmac_desc(vd); in milbeaut_xdmac_next_desc()
108 return mc->md; in milbeaut_xdmac_next_desc()
111 /* mc->vc.lock must be held by caller */
112 static void milbeaut_chan_start(struct milbeaut_xdmac_chan *mc, in milbeaut_chan_start() argument
119 writel_relaxed(val, mc->reg_ch_base + M10V_XDTBC); in milbeaut_chan_start()
122 writel_relaxed(val, mc->reg_ch_base + M10V_XDSSA); in milbeaut_chan_start()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A Dbase.c32 struct nvkm_mc *mc = device->mc; in nvkm_mc_unk260() local
33 if (likely(mc) && mc->func->unk260) in nvkm_mc_unk260()
34 mc->func->unk260(mc, data); in nvkm_mc_unk260()
53 struct nvkm_mc *mc = device->mc; in nvkm_mc_reset_mask() local
56 if (likely(mc)) { in nvkm_mc_reset_mask()
58 for (map = mc->func->reset; map && map->stat; map++) { in nvkm_mc_reset_mask()
76 device->mc->func->device->disable(device->mc, pmc_enable); in nvkm_mc_reset()
77 device->mc->func->device->enable(device->mc, pmc_enable); in nvkm_mc_reset()
86 device->mc->func->device->disable(device->mc, pmc_enable); in nvkm_mc_disable()
94 device->mc->func->device->enable(device->mc, pmc_enable); in nvkm_mc_enable()
[all …]
H A DKbuild2 nvkm-y += nvkm/subdev/mc/base.o
3 nvkm-y += nvkm/subdev/mc/nv04.o
4 nvkm-y += nvkm/subdev/mc/nv11.o
5 nvkm-y += nvkm/subdev/mc/nv17.o
6 nvkm-y += nvkm/subdev/mc/nv44.o
7 nvkm-y += nvkm/subdev/mc/nv50.o
8 nvkm-y += nvkm/subdev/mc/g84.o
9 nvkm-y += nvkm/subdev/mc/g98.o
10 nvkm-y += nvkm/subdev/mc/gt215.o
11 nvkm-y += nvkm/subdev/mc/gf100.o
[all …]
H A Dnv04.c34 nv04_mc_device_disable(struct nvkm_mc *mc, u32 mask) in nv04_mc_device_disable() argument
36 nvkm_mask(mc->subdev.device, 0x000200, mask, 0x00000000); in nv04_mc_device_disable()
40 nv04_mc_device_enable(struct nvkm_mc *mc, u32 mask) in nv04_mc_device_enable() argument
42 struct nvkm_device *device = mc->subdev.device; in nv04_mc_device_enable()
49 nv04_mc_device_enabled(struct nvkm_mc *mc, u32 mask) in nv04_mc_device_enabled() argument
51 return (nvkm_rd32(mc->subdev.device, 0x000200) & mask) == mask; in nv04_mc_device_enabled()
74 struct nvkm_mc *mc = container_of(intr, typeof(*mc), intr); in nv04_mc_intr_rearm() local
78 nvkm_wr32(mc->subdev.device, 0x000140 + (leaf * 4), 0x00000001); in nv04_mc_intr_rearm()
84 struct nvkm_mc *mc = container_of(intr, typeof(*mc), intr); in nv04_mc_intr_unarm() local
88 nvkm_wr32(mc->subdev.device, 0x000140 + (leaf * 4), 0x00000000); in nv04_mc_intr_unarm()
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-devices-edac1 What: /sys/devices/system/edac/mc/mc*/reset_counters
12 What: /sys/devices/system/edac/mc/mc*/seconds_since_reset
19 What: /sys/devices/system/edac/mc/mc*/mc_name
25 What: /sys/devices/system/edac/mc/mc*/size_mb
31 What: /sys/devices/system/edac/mc/mc*/ue_count
39 What: /sys/devices/system/edac/mc/mc*/ue_noinfo_count
46 What: /sys/devices/system/edac/mc/mc*/ce_count
56 What: /sys/devices/system/edac/mc/mc*/ce_noinfo_count
66 What: /sys/devices/system/edac/mc/mc*/sdram_scrub_rate
78 What: /sys/devices/system/edac/mc/mc*/max_location
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/linux/drivers/irqchip/
H A Dirq-riscv-aplic-msi.c84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg() local
105 tbppn &= ~APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); in aplic_msi_write_msg()
106 tbppn &= ~APLIC_xMSICFGADDR_PPN_LHX(mc->lhxw, mc->lhxs); in aplic_msi_write_msg()
107 tbppn &= ~APLIC_xMSICFGADDR_PPN_HHX(mc->hhxw, mc->hhxs); in aplic_msi_write_msg()
108 WARN_ON(tbppn != mc->base_ppn); in aplic_msi_write_msg()
111 group_index = (tppn >> APLIC_xMSICFGADDR_PPN_HHX_SHIFT(mc->hhxs)) & in aplic_msi_write_msg()
112 APLIC_xMSICFGADDR_PPN_HHX_MASK(mc->hhxw); in aplic_msi_write_msg()
113 hart_index = (tppn >> APLIC_xMSICFGADDR_PPN_LHX_SHIFT(mc->lhxs)) & in aplic_msi_write_msg()
114 APLIC_xMSICFGADDR_PPN_LHX_MASK(mc->lhxw); in aplic_msi_write_msg()
115 hart_index |= (group_index << mc->lhxw); in aplic_msi_write_msg()
[all …]
/linux/drivers/crypto/amlogic/
H A Damlogic-gxl-cipher.c20 static int get_engine_number(struct meson_dev *mc) in get_engine_number() argument
22 return atomic_inc_return(&mc->flow) % MAXFLOW; in get_engine_number()
89 struct meson_dev *mc = op->mc; in meson_cipher() local
106 dev_dbg(mc->dev, "%s %s %u %x IV(%u) key=%u flow=%d\n", __func__, in meson_cipher()
114 mc->chanlist[flow].stat_req++; in meson_cipher()
132 dev_err(mc->dev, "invalid ivsize=%d vs len=%d\n", ivsize, areq->cryptlen); in meson_cipher()
152 phykeyiv = dma_map_single(mc->dev, bkeyiv, keyivlen, in meson_cipher()
154 err = dma_mapping_error(mc->dev, phykeyiv); in meson_cipher()
156 dev_err(mc->dev, "Cannot DMA MAP KEY IV\n"); in meson_cipher()
164 desc = &mc->chanlist[flow].tl[tloffset]; in meson_cipher()
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/linux/drivers/bus/fsl-mc/
H A Dmc-io.c8 #include <linux/fsl/mc.h>
10 #include "fsl-mc-private.h"
53 * fsl_create_mc_io() - Creates an MC I/O object
55 * @dev: device to be associated with the MC I/O object
56 * @mc_portal_phys_addr: physical address of the MC portal to use
57 * @mc_portal_size: size in bytes of the MC portal
58 * @dpmcp_dev: Pointer to the DPMCP object associated with this MC I/O
60 * @flags: flags for the new MC I/O object
61 * @new_mc_io: Area to return pointer to newly created MC I/O object
95 "devm_request_mem_region failed for MC portal %pa\n", in fsl_create_mc_io()
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H A Dfsl-mc-bus.c3 * Freescale Management Complex (MC) bus driver
11 #define pr_fmt(fmt) "fsl-mc: " fmt
26 #include "fsl-mc-private.h"
29 * Default DMA mask for devices on a fsl-mc bus
36 * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
37 * @root_mc_bus_dev: fsl-mc device representing the root DPRC
52 * @mc_region_type: Type of MC region for the range being translated
53 * @start_mc_offset: Start MC offset of the range being translated
54 * @end_mc_offset: MC offset of the first byte after the range (last MC
77 * @dev: the fsl-mc device to match against
[all …]
H A DMakefile3 # Freescale Management Complex (MC) bus drivers
7 obj-$(CONFIG_FSL_MC_BUS) += mc-bus-driver.o
9 mc-bus-driver-objs := fsl-mc-bus.o \
10 mc-sys.o \
11 mc-io.o \
16 fsl-mc-allocator.o \
17 fsl-mc-msi.o \
21 # MC userspace support
22 obj-$(CONFIG_FSL_MC_UAPI_SUPPORT) += fsl-mc-uapi.o
H A Ddprc.c8 #include <linux/fsl/mc.h>
10 #include "fsl-mc-private.h"
14 * towards the mc firmware
21 * @mc_io: Pointer to MC portal's I/O object
45 /* send command to mc*/ in dprc_open()
59 * @mc_io: Pointer to MC portal's I/O object
78 /* send command to mc*/ in dprc_close()
85 * @mc_io: Pointer to MC portal's I/O object
136 * MC API 6.5 introduced a new field in the command used to pass in dprc_reset_container()
149 /* send command to mc*/ in dprc_reset_container()
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
54 - fsl,qoriq-mc
56 Must be "fsl,qoriq-mc". A Freescale Management Complex
59 the MC control register region.
68 the second region is the MC control registers. This
75 MC address space and the parent system address space.
77 The MC address space is defined by 3 components:
[all …]
/linux/include/linux/fsl/
H A Dmc.h3 * Freescale Management Complex (MC) bus public interface
27 * struct fsl_mc_driver - MC object device driver object
62 * enum fsl_mc_pool_type - Types of allocatable MC bus resources
68 FSL_MC_POOL_DPMCP = 0x0, /* corresponds to "dpmcp" in the MC */
69 FSL_MC_POOL_DPBP, /* corresponds to "dpbp" in the MC */
70 FSL_MC_POOL_DPCON, /* corresponds to "dpcon" in the MC */
80 * struct fsl_mc_resource - MC generic resource
82 * @id: unique MC resource Id within the resources of the same type
90 * MC resource structures.
101 * struct fsl_mc_device_irq - MC object device message-based interrupt
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gmc.c207 * @mc: memory controller structure holding memory information
213 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, in amdgpu_gmc_vram_location() argument
219 mc->vram_start = base; in amdgpu_gmc_vram_location()
220 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in amdgpu_gmc_vram_location()
221 if (limit < mc->real_vram_size) in amdgpu_gmc_vram_location()
222 mc->real_vram_size = limit; in amdgpu_gmc_vram_location()
224 if (vis_limit && vis_limit < mc->visible_vram_size) in amdgpu_gmc_vram_location()
225 mc->visible_vram_size = vis_limit; in amdgpu_gmc_vram_location()
227 if (mc->real_vram_size < mc->visible_vram_size) in amdgpu_gmc_vram_location()
228 mc->visible_vram_size = mc->real_vram_size; in amdgpu_gmc_vram_location()
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/linux/drivers/gpu/drm/radeon/
H A Dr520.c89 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); in r520_gpu_init()
97 rdev->mc.vram_width = 128; in r520_vram_get_type()
98 rdev->mc.vram_is_ddr = true; in r520_vram_get_type()
102 rdev->mc.vram_width = 32; in r520_vram_get_type()
105 rdev->mc.vram_width = 64; in r520_vram_get_type()
108 rdev->mc.vram_width = 128; in r520_vram_get_type()
111 rdev->mc.vram_width = 256; in r520_vram_get_type()
114 rdev->mc.vram_width = 128; in r520_vram_get_type()
118 rdev->mc.vram_width *= 2; in r520_vram_get_type()
126 radeon_vram_location(rdev, &rdev->mc, 0); in r520_mc_init()
[all …]
/linux/include/soc/tegra/
H A Dmc.h103 struct tegra_mc *mc);
108 struct tegra_mc *mc) in tegra_smmu_probe() argument
128 int (*hotreset_assert)(struct tegra_mc *mc,
130 int (*hotreset_deassert)(struct tegra_mc *mc,
132 int (*block_dma)(struct tegra_mc *mc,
134 bool (*dma_idling)(struct tegra_mc *mc,
136 int (*unblock_dma)(struct tegra_mc *mc,
138 int (*reset_status)(struct tegra_mc *mc,
164 int (*probe)(struct tegra_mc *mc);
165 void (*remove)(struct tegra_mc *mc);
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/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpni.c8 #include <linux/fsl/mc.h>
80 * @mc_io: Pointer to MC portal's I/O object
89 * associated with the specific object ID and the specific MC
112 /* send command to mc*/ in dpni_open()
125 * @mc_io: Pointer to MC portal's I/O object
145 /* send command to mc*/ in dpni_close()
151 * @mc_io: Pointer to MC portal's I/O object
188 /* send command to mc*/ in dpni_set_pools()
194 * @mc_io: Pointer to MC portal's I/O object
211 /* send command to mc*/ in dpni_enable()
[all …]

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