| /linux/Documentation/networking/ |
| H A D | oa-tc6-framework.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
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| H A D | sfp-phylink.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 phylink is a mechanism to support hot-pluggable networking modules
11 directly connected to a MAC without needing to re-initialise the
12 adapter on hot-plug events.
14 phylink supports conventional phylib-based setups, fixed link setups
23 1. PHY mode
25 In PHY mode, we use phylib to read the current link settings from
26 the PHY, and pass them to the MAC driver. We expect the MAC driver
32 Fixed mode is the same as PHY mode as far as the MAC driver is
35 3. In-band mode
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| H A D | phy.rst | 2 PHY Abstraction Layer
9 to a MAC layer, which communicates with the physical connection through a
10 PHY. The PHY concerns itself with negotiating link parameters with the link
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
30 Basically, this layer is meant to provide an interface to PHY devices which
37 Most network devices are connected to a PHY by means of a management bus.
47 mii_id is the address on the bus for the PHY, and regnum is the register
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
21 Specifies the MAC address that was assigned to the network device.
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
28 Specifies the MAC address that was last used by the boot
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| H A D | hisilicon-femac.txt | 1 Hisilicon Fast Ethernet MAC controller
4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
9 The first region is the MAC core register base and size.
10 The second region is the global MAC control register.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
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| H A D | engleder,tsnep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TSN endpoint Ethernet MAC
10 - Gerhard Engleder <gerhard@engleder-embedded.com>
13 - $ref: ethernet-controller.yaml#
26 interrupt-names:
29 - const: mac
30 - const: txrx-1
31 - const: txrx-2
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| H A D | cpsw.txt | 2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
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| H A D | hisilicon-hix5hd2-gmac.txt | 4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
14 The first region is the MAC register base and size.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
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| H A D | qcom-emac.txt | 3 This network controller consists of two devices: a MAC and an SGMII
4 internal PHY. Each device is represented by a device tree node. A phandle
5 connects the MAC node to its corresponding internal phy node. Another
6 phandle points to the external PHY node.
10 MAC node:
11 - compatible : Should be "qcom,fsm9900-emac".
12 - reg : Offset and length of the register regions for the device
13 - interrupts : Interrupt number used by this controller
14 - mac-address : The 6-byte MAC address. If present, it is the default
15 MAC address.
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| H A D | faraday,ftgmac100.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Po-Yu Chuang <ratbert@faraday-tech.com>
18 - const: faraday,ftgmac100
19 - items:
20 - enum:
21 - aspeed,ast2400-mac
22 - aspeed,ast2500-mac
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| H A D | sunplus,sp7021-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/sunplus,sp7021-emac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 Dual Ethernet MAC
11 - Wells Lu <wellslutw@gmail.com>
14 Sunplus SP7021 dual 10M/100M Ethernet MAC controller.
19 const: sunplus,sp7021-emac
33 ethernet-ports:
36 description: Ethernet ports to PHY
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| /linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | 82571.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
42 * e1000_init_phy_params_82571 - Init PHY func ptrs.
47 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82571() local
50 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82571()
51 phy->type = e1000_phy_none; in e1000_init_phy_params_82571()
55 phy->addr = 1; in e1000_init_phy_params_82571()
56 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82571()
57 phy->reset_delay_us = 100; in e1000_init_phy_params_82571()
59 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82571()
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| H A D | ich8lan.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
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| H A D | 80003es2lan.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
35 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
40 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_80003es2lan() local
43 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_80003es2lan()
44 phy->type = e1000_phy_none; in e1000_init_phy_params_80003es2lan()
47 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_80003es2lan()
48 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; in e1000_init_phy_params_80003es2lan()
51 phy->addr = 1; in e1000_init_phy_params_80003es2lan()
52 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_80003es2lan()
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| /linux/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_82575.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap() local
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| /linux/drivers/net/ethernet/chelsio/cxgb/ |
| H A D | subr.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
40 * t1_wait_op_done - wait until an operation is completed
43 * @mask: a single-bit field within @reg that indicates completion
56 u32 val = readl(adapter->regs + reg) & mask; in t1_wait_op_done()
60 if (--attempts == 0) in t1_wait_op_done()
76 writel(addr, adapter->regs + A_TPI_ADDR); in __t1_tpi_write()
77 writel(value, adapter->regs + A_TPI_WR_DATA); in __t1_tpi_write()
78 writel(F_TPIWR, adapter->regs + A_TPI_CSR); in __t1_tpi_write()
84 adapter->name, addr); in __t1_tpi_write()
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| /linux/drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe_82599.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
65 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599() local
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
72 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
74 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
78 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
79 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
80 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
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| /linux/drivers/net/ethernet/intel/igc/ |
| H A D | igc_base.c | 1 // SPDX-License-Identifier: GPL-2.0
13 * igc_reset_hw_base - Reset hardware
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_base()
25 * on the last TLP read/write transaction when MAC is reset. in igc_reset_hw_base()
29 hw_dbg("PCI-E Master disable polling has failed\n"); in igc_reset_hw_base()
42 hw_dbg("Issuing a global reset to MAC\n"); in igc_reset_hw_base()
62 * igc_init_nvm_params_base - Init NVM func ptrs.
67 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_base()
73 /* Added to a constant, "size" becomes the left-shift value in igc_init_nvm_params_base()
84 nvm->type = igc_nvm_eeprom_spi; in igc_init_nvm_params_base()
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| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-j784s4-evm-quad-port-eth-exp1.dtso | 1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
4 * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
11 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
14 /dts-v1/;
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/phy/phy-cadence.h>
19 #include <dt-bindings/phy/phy.h>
21 #include "k3-pinctrl.h"
22 #include "k3-serdes.h"
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| /linux/net/core/ |
| H A D | of_net.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/phy.h>
15 #include <linux/nvmem-consumer.h>
18 * of_get_phy_mode - Get phy mode for given device_node
22 * The function gets phy interface string from property 'phy-mode' or
23 * 'phy-connection-type'. The index in phy_modes table is set in
25 * PHY_INTERFACE_MODE_NA and an errno is returned, e.g. -ENODEV.
34 err = of_property_read_string(np, "phy-mode", &pm); in of_get_phy_mode()
36 err = of_property_read_string(np, "phy-connection-type", &pm); in of_get_phy_mode()
46 return -ENODEV; in of_get_phy_mode()
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| /linux/arch/mips/boot/dts/cavium-octeon/ |
| H A D | octeon_3xxx.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
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| /linux/Documentation/firmware-guide/acpi/dsd/ |
| H A D | phy.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 The PHYs on an MDIO bus [phy] are probed and registered using
14 for connecting PHYs on the MDIO bus [dsd-properties-rules] to the MAC layer.
17 Properties UUID For _DSD" [dsd-guide] document and the
18 daffd814-6eba-4d8c-8a91-bc9bbf4aa301 UUID must be used in the Device
21 phy-handle
22 ----------
23 For each MAC node, a device property "phy-handle" is used to reference
24 the PHY that is registered on an MDIO bus. This is mandatory for
25 network interfaces that have PHYs connected to MAC via MDIO bus.
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls1028a-kontron-kbox-a-230-ls.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree File for the Kontron KBox A-230-LS.
5 * This consists of a Kontron SMARC-sAL28 (Dual PHY) and a special
12 /dts-v1/;
13 #include "fsl-ls1028a-kontron-sl28-var4.dts"
14 #include <dt-bindings/leds/common.h>
17 model = "Kontron KBox A-230-LS";
18 compatible = "kontron,kbox-a-230-ls", "kontron,sl28-var4",
22 compatible = "gpio-leds";
24 alarm-led {
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| /linux/include/linux/ |
| H A D | phylink.h | 4 #include <linux/phy.h>
21 MLO_AN_PHY = 0, /* Conventional PHY */
22 MLO_AN_FIXED, /* Fixed-link mode */
23 MLO_AN_INBAND, /* In-band protocol */
26 * PHYLINK_PCS_NEG_NONE - protocol has no inband capability
27 * PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
28 * PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
29 * 1000base-X with autoneg off
30 * PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
32 * PHYLINK_PCS_NEG_INBAND - inband mode selected
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| /linux/drivers/net/ethernet/altera/ |
| H A D | altera_tse.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
29 #include <linux/phy.h>
48 /* MAC function configuration default settings */
55 /* MAC Command_Config Register Bit Definitions
113 /* MDIO registers within MAC register Space
116 u32 control; /* PHY device operation control register */
117 u32 status; /* PHY device operation status register */
118 u32 phy_id1; /* Bits 31:16 of PHY identifier */
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