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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_color.c71 * - Input gamma LUT (de-normalized)
73 * - Surface degamma LUT (normalized)
75 * - Surface regamma LUT (normalized)
84 * The input gamma LUT block isn't really applicable here since it
99 * their respective property is set to NULL. A linear DGM/RGM LUT should
143 * 5. 1D LUT
144 * 6. 3D LUT
146 * 8. 1D LUT
159 * The 3DLUT (#6) is a tetrahedrally interpolated 17 cube LUT.
198 * degamma TF, shaper TF (before 3D LUT), an
459 __is_lut_linear(const struct drm_color_lut * lut,uint32_t size) __is_lut_linear() argument
488 __drm_lut_to_dc_gamma(const struct drm_color_lut * lut,struct dc_gamma * gamma,bool is_legacy) __drm_lut_to_dc_gamma() argument
526 __drm_lut32_to_dc_gamma(const struct drm_color_lut32 * lut,struct dc_gamma * gamma) __drm_lut32_to_dc_gamma() argument
604 __set_legacy_tf(struct dc_transfer_func * func,const struct drm_color_lut * lut,uint32_t lut_size,bool has_rom) __set_legacy_tf() argument
642 __set_output_tf(struct dc_transfer_func * func,const struct drm_color_lut * lut,uint32_t lut_size,bool has_rom) __set_output_tf() argument
700 __set_output_tf_32(struct dc_transfer_func * func,const struct drm_color_lut32 * lut,uint32_t lut_size,bool has_rom) __set_output_tf_32() argument
794 __set_input_tf(struct dc_color_caps * caps,struct dc_transfer_func * func,const struct drm_color_lut * lut,uint32_t lut_size) __set_input_tf() argument
830 __set_input_tf_32(struct dc_color_caps * caps,struct dc_transfer_func * func,const struct drm_color_lut32 * lut,uint32_t lut_size) __set_input_tf_32() argument
905 __to_dc_lut3d_color(struct dc_rgb * rgb,const struct drm_color_lut lut,int bit_precision) __to_dc_lut3d_color() argument
913 __drm_3dlut_to_dc_3dlut(const struct drm_color_lut * lut,uint32_t lut3d_size,struct tetrahedral_params * params,bool use_tetrahedral_9,int bit_depth) __drm_3dlut_to_dc_3dlut() argument
958 __to_dc_lut3d_32_color(struct dc_rgb * rgb,const struct drm_color_lut32 lut,int bit_precision) __to_dc_lut3d_32_color() argument
966 __drm_3dlut32_to_dc_3dlut(const struct drm_color_lut32 * lut,uint32_t lut3d_size,struct tetrahedral_params * params,bool use_tetrahedral_9,int bit_depth) __drm_3dlut32_to_dc_3dlut() argument
1020 amdgpu_dm_atomic_lut3d(const struct drm_color_lut * drm_lut3d,uint32_t drm_lut3d_size,struct dc_3dlut * lut) amdgpu_dm_atomic_lut3d() argument
1149 const struct drm_color_lut *lut = NULL; amdgpu_dm_verify_lut_sizes() local
1681 __set_colorop_3dlut(const struct drm_color_lut32 * drm_lut3d,uint32_t drm_lut3d_size,struct dc_3dlut * lut) __set_colorop_3dlut() argument
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H A Damdgpu_dm_colorop.c144 /* 1D LUT - SHAPER LUT */ in amdgpu_dm_initialize_default_pipeline()
163 /* 3D LUT */ in amdgpu_dm_initialize_default_pipeline()
199 /* 1D LUT - BLND LUT */ in amdgpu_dm_initialize_default_pipeline()
/linux/include/drm/
H A Ddrm_color_mgmt.h34 * drm_color_lut_extract - clamp and round LUT entries
36 * @bit_precision: number of bits the hw LUT supports
38 * Extract a degamma/gamma LUT value provided by user (in the form of
54 * drm_color_lut32_extract - clamp and round LUT entries
56 * @bit_precision: number of bits the hw LUT supports
58 * Extract U0.bit_precision from a U0.32 LUT value.
80 * drm_color_lut_size - calculate the number of entries in the LUT
81 * @blob: blob containing the LUT
84 * The number of entries in the color LUT stored in @blob.
92 * drm_color_lut32_size - calculate the number of entries in the extended LUT
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/linux/drivers/net/wireless/ath/ath11k/
H A Dcfr.c54 void ath11k_cfr_release_lut_entry(struct ath11k_look_up_table *lut) in ath11k_cfr_release_lut_entry() argument
56 memset(lut, 0, sizeof(*lut)); in ath11k_cfr_release_lut_entry()
77 struct ath11k_look_up_table *lut; in ath11k_cfr_free_pending_dbr_events() local
80 if (!cfr->lut) in ath11k_cfr_free_pending_dbr_events()
84 lut = &cfr->lut[i]; in ath11k_cfr_free_pending_dbr_events()
85 if (lut->dbr_recv && !lut->tx_recv && in ath11k_cfr_free_pending_dbr_events()
86 lut->dbr_tstamp < cfr->last_success_tstamp) { in ath11k_cfr_free_pending_dbr_events()
87 ath11k_dbring_bufs_replenish(ar, &cfr->rx_ring, lut->buff, in ath11k_cfr_free_pending_dbr_events()
89 ath11k_cfr_release_lut_entry(lut); in ath11k_cfr_free_pending_dbr_events()
98 * @lut: Lookup table for correlation
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/linux/drivers/gpu/drm/
H A Ddrm_color_mgmt.c44 * Blob property to set the degamma lookup table (LUT) mapping pixel data
47 * Hardware might choose not to use the full precision of the LUT elements
48 * nor use all the elements of the LUT (for example the hardware might
49 * choose to interpolate between LUT[0] and LUT[4]).
59 * hardware). If drivers support multiple LUT sizes then they should
65 * pixel data after the lookup through the degamma LUT and before the
66 * lookup through the gamma LUT. The data is interpreted as a struct
75 * Blob property to set the gamma lookup table (LUT) mapping pixel data
78 * Hardware might choose not to use the full precision of the LUT element
606 drm_color_lut_check(const struct drm_property_blob * lut,u32 tests) drm_color_lut_check() argument
651 drm_crtc_load_gamma_888(struct drm_crtc * crtc,const struct drm_color_lut * lut,drm_crtc_set_lut_func set_gamma) drm_crtc_load_gamma_888() argument
671 drm_crtc_load_gamma_565_from_888(struct drm_crtc * crtc,const struct drm_color_lut * lut,drm_crtc_set_lut_func set_gamma) drm_crtc_load_gamma_565_from_888() argument
701 drm_crtc_load_gamma_555_from_888(struct drm_crtc * crtc,const struct drm_color_lut * lut,drm_crtc_set_lut_func set_gamma) drm_crtc_load_gamma_555_from_888() argument
810 drm_crtc_load_palette_8(struct drm_crtc * crtc,const struct drm_color_lut * lut,drm_crtc_set_lut_func set_palette) drm_crtc_load_palette_8() argument
889 drm_color_lut32_check(const struct drm_property_blob * lut,u32 tests) drm_color_lut32_check() argument
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mode.h350 /* @plane_degamma_lut_property: Plane property to set a degamma LUT to
356 * size of degamma LUT as supported by the driver (read-only).
372 * shaper LUT that converts color content before 3D LUT.
374 * combine the user LUT values with pre-defined TF into the LUT
380 * pre-blending shaper LUT as supported by the driver (read-only).
385 * transfer function for pre-blending shaper (before applying 3D LUT)
386 * with or without LUT. There is no shaper ROM, but we can use AMD
387 * color modules to program LUT parameter
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/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dlut.c22 #include "lut.h"
32 nv50_lut_load(struct nv50_lut *lut, int buffer, struct drm_property_blob *blob, in nv50_lut_load() argument
36 void __iomem *mem = lut->mem[buffer].object.map.ptr; in nv50_lut_load()
37 const u32 addr = lut->mem[buffer].addr; in nv50_lut_load()
59 nv50_lut_fini(struct nv50_lut *lut) in nv50_lut_fini() argument
62 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) in nv50_lut_fini()
63 nvif_mem_dtor(&lut->mem[i]); in nv50_lut_fini()
68 struct nv50_lut *lut) in nv50_lut_init() argument
72 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) { in nv50_lut_init()
74 size * 8, &lut->mem[i]); in nv50_lut_init()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_color.c193 static bool lut_is_legacy(const struct drm_property_blob *lut) in lut_is_legacy() argument
195 return lut && drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; in lut_is_legacy()
546 * On GLK both pipe CSC and degamma LUT are controlled in ilk_assign_csc()
548 * LUT is needed but CSC is not we need to load an in ilk_assign_csc()
820 /* convert hw value with given bit_precision to lut property val */
1200 struct drm_color_lut *lut; in create_linear_lut()
1204 sizeof(lut[0]) * lut_size, in create_linear_lut()
1209 lut = blob->data; in create_linear_lut()
1214 lut[ in lut_limited_range()
1191 struct drm_color_lut *lut; create_linear_lut() local
1260 const struct drm_color_lut *lut; i9xx_load_lut_8() local
1278 const struct drm_color_lut *lut = blob->data; i9xx_load_lut_10() local
1314 const struct drm_color_lut *lut = blob->data; i965_load_lut_10p6() local
1376 const struct drm_color_lut *lut; ilk_load_lut_8() local
1415 const struct drm_color_lut *lut = blob->data; ilk_load_lut_10() local
1461 const struct drm_color_lut *lut = blob->data; ivb_load_lut_10() local
1486 const struct drm_color_lut *lut = blob->data; bdw_load_lut_10() local
1622 const struct drm_color_lut *lut = blob->data; glk_load_degamma_lut() local
1706 const struct drm_color_lut *lut = blob->data; icl_program_gamma_superfine_segment() local
1741 const struct drm_color_lut *lut = blob->data; icl_program_gamma_multi_segment() local
1861 const struct drm_color_lut *lut = blob->data; chv_load_cgm_degamma() local
1895 const struct drm_color_lut *lut = blob->data; chv_load_cgm_gamma() local
2241 check_lut_size(struct intel_crtc * crtc,const char * lut_name,const struct drm_property_blob * lut,int expected) check_lut_size() argument
2317 const struct drm_color_lut *lut = blob->data; i9xx_check_lut_10() local
3301 struct drm_color_lut *lut; i9xx_read_lut_8() local
3328 struct drm_color_lut *lut; i9xx_read_lut_10() local
3379 struct drm_color_lut *lut; i965_read_lut_10p6() local
3431 struct drm_color_lut *lut; chv_read_cgm_degamma() local
3457 struct drm_color_lut *lut; chv_read_cgm_gamma() local
3505 struct drm_color_lut *lut; ilk_read_lut_8() local
3531 struct drm_color_lut *lut; ilk_read_lut_10() local
3594 struct drm_color_lut *lut; ivb_read_lut_10() local
3659 struct drm_color_lut *lut; bdw_read_lut_10() local
3724 struct drm_color_lut *lut; glk_read_degamma_lut() local
3790 struct drm_color_lut *lut; icl_read_lut_multi_segment() local
4077 const struct drm_color_lut32 *lut = blob->data; glk_load_lut_3d() local
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/linux/drivers/gpio/
H A Dgpio-adp5520.c19 unsigned char lut[ADP5520_MAXGPIOS]; member
40 return !!(reg_val & dev->lut[off]); in adp5520_gpio_get_value()
51 dev->lut[off]); in adp5520_gpio_set_value()
54 dev->lut[off]); in adp5520_gpio_set_value()
65 dev->lut[off]); in adp5520_gpio_direction_input()
79 dev->lut[off]); in adp5520_gpio_direction_output()
82 dev->lut[off]); in adp5520_gpio_direction_output()
85 dev->lut[off]); in adp5520_gpio_direction_output()
116 dev->lut[gpios++] = 1 << i; in adp5520_gpio_probe()
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A DMSS_Ingress_registers.h50 * (IGPRCTLF) LUT
51 * 0x1 : Ingress Pre-Security Classification LUT (IGPRC)
52 * 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT
53 * 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT
54 * 0x4 : Ingress Post-Security Classification LUT
57 * (IGPOCTLF) LUT
H A DMSS_Egress_registers.h51 /* 0x0 : Egress MAC Control FIlter (CTLF) LUT
52 * 0x1 : Egress Classification LUT
53 * 0x2 : Egress SC/SA LUT
/linux/Documentation/gpu/rfc/
H A Dcolor_pipeline.rst126 * custom (uniform) 1D LUT
129 * 3D LUT
147 …├─ "TYPE": immutable enum {1D enumerated curve, 1D LUT, 3x3 matrix, 3x4 matrix, 3D LUT, etc.} = 1D…
152 /* custom 4k entry 1D LUT */
154 …├─ "TYPE": immutable enum {1D enumerated curve, 1D LUT, 3x3 matrix, 3x4 matrix, 3D LUT, etc.} = 1D…
160 /* 17^3 3D LUT */
162 …├─ "TYPE": immutable enum {1D enumerated curve, 1D LUT, 3x3 matrix, 3x4 matrix, 3D LUT, etc.} = 3D…
266 ├─ "TYPE" (immutable) = 1D LUT
272 ├─ "TYPE" (immutable) = 3D LUT
/linux/drivers/clk/rockchip/
H A Dsoftrst.c15 const int *lut; member
31 if (softrst->lut) in rockchip_softrst_assert()
32 id = softrst->lut[id]; in rockchip_softrst_assert()
63 if (softrst->lut) in rockchip_softrst_deassert()
64 id = softrst->lut[id]; in rockchip_softrst_deassert()
106 softrst->lut = lookup_table; in rockchip_register_softrst_lut()
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_aal.c82 * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL
85 * Return: 0 if gamma control not supported in AAL or gamma LUT size
99 struct drm_color_lut *lut; in mtk_aal_gamma_set() local
107 /* Also, if there's no gamma lut there's nothing to do here. */ in mtk_aal_gamma_set()
111 lut = (struct drm_color_lut *)state->gamma_lut->data; in mtk_aal_gamma_set()
114 .red = drm_color_lut_extract(lut[i].red, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
115 .green = drm_color_lut_extract(lut[i].green, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
116 .blue = drm_color_lut_extract(lut[i].blue, DISP_AAL_LUT_BITS) in mtk_aal_gamma_set()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dspp.h41 * struct dpu_hw_gc_lut - gc lut feature structure
44 * @c0: color0 component lut
45 * @c1: color1 component lut
46 * @c2: color2 component lut
71 * @gc_lut: Pointer to lut content
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_common.c259 * @lut: pointer to the lut buffer provided by the caller
260 * @lut_size: size of the lut buffer
267 u8 *lut, u16 lut_size, in iavf_aq_get_set_rss_lut() argument
301 status = iavf_asq_send_command(hw, &desc, lut, lut_size, NULL); in iavf_aq_get_set_rss_lut()
311 * @lut: pointer to the lut buffer provided by the caller
312 * @lut_size: size of the lut buffer
317 bool pf_lut, u8 *lut, u16 lut_size) in iavf_aq_set_rss_lut() argument
319 return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); in iavf_aq_set_rss_lut()
/linux/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c126 struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data; in malidp_generate_gamma_table() local
134 out_start = drm_color_lut_extract(lut[segments[i].start].green, in malidp_generate_gamma_table()
136 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12); in malidp_generate_gamma_table()
144 * Check if there is a new gamma LUT and if it is of an acceptable size. Also,
151 struct drm_color_lut *lut; in malidp_crtc_atomic_check_gamma() local
169 lut = (struct drm_color_lut *)state->gamma_lut->data; in malidp_crtc_atomic_check_gamma()
171 if (!((lut[i].red == lut[i].green) && in malidp_crtc_atomic_check_gamma()
172 (lut[i].red == lut[ in malidp_crtc_atomic_check_gamma()
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/linux/drivers/hwmon/
H A Dmax31760.c47 } lut[LUT_SIZE]; member
491 struct lut_attribute *lut; in max31760_create_lut_nodes() local
494 lut = &state->lut[i]; in max31760_create_lut_nodes()
495 sda = &lut->sda; in max31760_create_lut_nodes()
497 snprintf(lut->name, sizeof(lut->name), in max31760_create_lut_nodes()
504 sda->dev_attr.attr.name = lut->name; in max31760_create_lut_nodes()
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6115-dpu.yaml33 - description: Display lut
42 - const: lut
73 clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
H A Dqcom,qcm2290-dpu.yaml33 - description: Display lut clock from dispcc
41 - const: lut
70 clock-names = "bus", "iface", "core", "lut", "vsync";
H A Dqcom,sc7180-dpu.yaml38 - description: Display lut clock
49 - const: lut
98 clock-names = "bus", "iface", "rot", "lut", "core",
H A Dqcom,sm7150-dpu.yaml33 - description: Display lut clock
42 - const: lut
75 "lut",
H A Dqcom,sm8650-dpu.yaml45 - description: Display lut
53 - const: lut
84 "lut",
/linux/Documentation/hwmon/
H A Dmax31760.rst28 reading as an index to a 48-byte lookup table (LUT) containing
29 user-programmed PWM values. The flexible LUT-based architecture enables
47 LUT Index Name
75 pwm1_auto_point[1-48]_pwm PWM value for LUT point
/linux/drivers/net/wireless/ti/wl1251/
H A Dboot.c70 static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = { in wl1251_boot_init_seq() local
143 tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000; in wl1251_boot_init_seq()
149 tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER]; in wl1251_boot_init_seq()
160 tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) | in wl1251_boot_init_seq()
161 (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1; in wl1251_boot_init_seq()
168 tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000; in wl1251_boot_init_seq()
176 tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030; in wl1251_boot_init_seq()

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