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/linux/drivers/media/platform/renesas/vsp1/
H A Dvsp1_lut.c28 static inline void vsp1_lut_write(struct vsp1_lut *lut, in vsp1_lut_write() argument
40 static int lut_set_table(struct vsp1_lut *lut, struct v4l2_ctrl *ctrl) in lut_set_table() argument
45 dlb = vsp1_dl_body_get(lut->pool); in lut_set_table()
53 spin_lock_irq(&lut->lock); in lut_set_table()
54 swap(lut->lut, dlb); in lut_set_table()
55 spin_unlock_irq(&lut->lock); in lut_set_table()
63 struct vsp1_lut *lut = in lut_s_ctrl() local
68 lut_set_table(lut, ctrl); in lut_s_ctrl()
154 struct vsp1_lut *lut = to_lut(&entity->subdev); in lut_configure_stream() local
156 vsp1_lut_write(lut, dlb, VI6_LUT_CTRL, VI6_LUT_CTRL_EN); in lut_configure_stream()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_color.c68 * - Input gamma LUT (de-normalized)
70 * - Surface degamma LUT (normalized)
72 * - Surface regamma LUT (normalized)
81 * The input gamma LUT block isn't really applicable here since it
96 * their respective property is set to NULL. A linear DGM/RGM LUT should
140 * 5. 1D LUT
141 * 6. 3D LUT
143 * 8. 1D LUT
156 * The 3DLUT (#6) is a tetrahedrally interpolated 17 cube LUT.
195 * degamma TF, shaper TF (before 3D LUT), and blend(dpp.ogam) TF and
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H A Damdgpu_dm_colorop.c134 /* 1D LUT - SHAPER LUT */ in amdgpu_dm_initialize_default_pipeline()
151 /* 3D LUT */ in amdgpu_dm_initialize_default_pipeline()
186 /* 1D LUT - BLND LUT */ in amdgpu_dm_initialize_default_pipeline()
/linux/include/drm/
H A Ddrm_color_mgmt.h34 * drm_color_lut_extract - clamp and round LUT entries
36 * @bit_precision: number of bits the hw LUT supports
38 * Extract a degamma/gamma LUT value provided by user (in the form of
54 * drm_color_lut32_extract - clamp and round LUT entries
56 * @bit_precision: number of bits the hw LUT supports
58 * Extract U0.bit_precision from a U0.32 LUT value.
80 * drm_color_lut_size - calculate the number of entries in the LUT
81 * @blob: blob containing the LUT
84 * The number of entries in the color LUT stored in @blob.
92 * drm_color_lut32_size - calculate the number of entries in the extended LUT
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/linux/drivers/net/wireless/ath/ath11k/
H A Dcfr.c54 void ath11k_cfr_release_lut_entry(struct ath11k_look_up_table *lut) in ath11k_cfr_release_lut_entry() argument
56 memset(lut, 0, sizeof(*lut)); in ath11k_cfr_release_lut_entry()
77 struct ath11k_look_up_table *lut; in ath11k_cfr_free_pending_dbr_events() local
80 if (!cfr->lut) in ath11k_cfr_free_pending_dbr_events()
84 lut = &cfr->lut[i]; in ath11k_cfr_free_pending_dbr_events()
85 if (lut->dbr_recv && !lut->tx_recv && in ath11k_cfr_free_pending_dbr_events()
86 lut->dbr_tstamp < cfr->last_success_tstamp) { in ath11k_cfr_free_pending_dbr_events()
87 ath11k_dbring_bufs_replenish(ar, &cfr->rx_ring, lut->buff, in ath11k_cfr_free_pending_dbr_events()
89 ath11k_cfr_release_lut_entry(lut); in ath11k_cfr_free_pending_dbr_events()
98 * @lut: Lookup table for correlation
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/linux/drivers/gpu/drm/
H A Ddrm_color_mgmt.c44 * Blob property to set the degamma lookup table (LUT) mapping pixel data
47 * Hardware might choose not to use the full precision of the LUT elements
48 * nor use all the elements of the LUT (for example the hardware might
49 * choose to interpolate between LUT[0] and LUT[4]).
59 * hardware). If drivers support multiple LUT sizes then they should
65 * pixel data after the lookup through the degamma LUT and before the
66 * lookup through the gamma LUT. The data is interpreted as a struct
75 * Blob property to set the gamma lookup table (LUT) mapping pixel data
78 * Hardware might choose not to use the full precision of the LUT elements
79 * nor use all the elements of the LUT (for example the hardware might
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H A Ddrm_colorop.c67 { DRM_COLOROP_1D_LUT, "1D LUT" },
70 { DRM_COLOROP_3D_LUT, "3D LUT"},
291 * @lut_size: LUT size supported by driver
292 * @interpolation: 1D LUT interpolation type
308 /* initialize 1D LUT only attribute */ in drm_plane_colorop_curve_1d_lut_init()
309 /* LUT size */ in drm_plane_colorop_curve_1d_lut_init()
405 /* LUT size */ in drm_plane_colorop_3dlut_init()
525 [DRM_COLOROP_1D_LUT] = "1D LUT",
528 [DRM_COLOROP_3D_LUT] = "3D LUT",
/linux/drivers/video/fbdev/
H A Dmacfb.c58 unsigned char lut; member
64 unsigned char lut; member
73 unsigned char lut; member
79 unsigned char lut; /* OFFSET: 0x10 */ member
101 unsigned char lut; member
106 unsigned char lut; /* TFBClutWDataReg, offset 0x90018 */ member
114 unsigned char lut; member
167 &dafb_cmap_regs->lut); in dafb_setpalette()
170 &dafb_cmap_regs->lut); in dafb_setpalette()
173 &dafb_cmap_regs->lut); in dafb_setpalette()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mode.h350 /* @plane_degamma_lut_property: Plane property to set a degamma LUT to
356 * size of degamma LUT as supported by the driver (read-only).
372 * shaper LUT that converts color content before 3D LUT.
374 * combine the user LUT values with pre-defined TF into the LUT
380 * pre-blending shaper LUT as supported by the driver (read-only).
385 * transfer function for pre-blending shaper (before applying 3D LUT)
386 * with or without LUT. There is no shaper ROM, but we can use AMD
387 * color modules to program LUT parameters from predefined TF (or
388 * from a combination of pre-defined TF and the custom 1D LUT).
393 * a 3D LUT (pre-blending), a three-dimensional array where each
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/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dlut.c22 #include "lut.h"
32 nv50_lut_load(struct nv50_lut *lut, int buffer, struct drm_property_blob *blob, in nv50_lut_load() argument
36 void __iomem *mem = lut->mem[buffer].object.map.ptr; in nv50_lut_load()
37 const u32 addr = lut->mem[buffer].addr; in nv50_lut_load()
59 nv50_lut_fini(struct nv50_lut *lut) in nv50_lut_fini() argument
62 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) in nv50_lut_fini()
63 nvif_mem_dtor(&lut->mem[i]); in nv50_lut_fini()
68 struct nv50_lut *lut) in nv50_lut_init() argument
72 for (i = 0; i < ARRAY_SIZE(lut->mem); i++) { in nv50_lut_init()
74 size * 8, &lut->mem[i]); in nv50_lut_init()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_color.c193 static bool lut_is_legacy(const struct drm_property_blob *lut) in lut_is_legacy() argument
195 return lut && drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; in lut_is_legacy()
546 * On GLK both pipe CSC and degamma LUT are controlled in ilk_assign_csc()
548 * LUT is needed but CSC is not we need to load an in ilk_assign_csc()
820 /* convert hw value with given bit_precision to lut property val */
1191 struct drm_color_lut *lut; in create_linear_lut() local
1195 sizeof(lut[0]) * lut_size, in create_linear_lut()
1200 lut = blob->data; in create_linear_lut()
1205 lut[i].red = val; in create_linear_lut()
1206 lut[i].green = val; in create_linear_lut()
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/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_cmm.h19 * @lut: 1D-LUT configuration
20 * @lut.table: 1D-LUT table entries. Disable LUT operations when NULL
25 } lut; member
/linux/drivers/gpio/
H A Dgpio-adp5520.c19 unsigned char lut[ADP5520_MAXGPIOS]; member
40 return !!(reg_val & dev->lut[off]); in adp5520_gpio_get_value()
51 dev->lut[off]); in adp5520_gpio_set_value()
54 dev->lut[off]); in adp5520_gpio_set_value()
65 dev->lut[off]); in adp5520_gpio_direction_input()
79 dev->lut[off]); in adp5520_gpio_direction_output()
82 dev->lut[off]); in adp5520_gpio_direction_output()
85 dev->lut[off]); in adp5520_gpio_direction_output()
116 dev->lut[gpios++] = 1 << i; in adp5520_gpio_probe()
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A DMSS_Ingress_registers.h50 * (IGPRCTLF) LUT
51 * 0x1 : Ingress Pre-Security Classification LUT (IGPRC)
52 * 0x2 : Ingress Packet Format (IGPFMT) SAKey LUT
53 * 0x3 : Ingress Packet Format (IGPFMT) SC/SA LUT
54 * 0x4 : Ingress Post-Security Classification LUT
57 * (IGPOCTLF) LUT
H A DMSS_Egress_registers.h51 /* 0x0 : Egress MAC Control FIlter (CTLF) LUT
52 * 0x1 : Egress Classification LUT
53 * 0x2 : Egress SC/SA LUT
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_surface.c243 struct dc_3dlut *lut = container_of(kref, struct dc_3dlut, refcount); in dc_3dlut_func_free() local
245 kvfree(lut); in dc_3dlut_func_free()
250 struct dc_3dlut *lut = kvzalloc_obj(*lut); in dc_create_3dlut_func() local
252 if (lut == NULL) in dc_create_3dlut_func()
255 kref_init(&lut->refcount); in dc_create_3dlut_func()
256 lut->state.raw = 0; in dc_create_3dlut_func()
258 return lut; in dc_create_3dlut_func()
265 void dc_3dlut_func_release(struct dc_3dlut *lut) in dc_3dlut_func_release() argument
267 kref_put(&lut->refcount, dc_3dlut_func_free); in dc_3dlut_func_release()
270 void dc_3dlut_func_retain(struct dc_3dlut *lut) in dc_3dlut_func_retain() argument
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/linux/Documentation/gpu/rfc/
H A Dcolor_pipeline.rst126 * custom (uniform) 1D LUT
129 * 3D LUT
147 …├─ "TYPE": immutable enum {1D enumerated curve, 1D LUT, 3x3 matrix, 3x4 matrix, 3D LUT, etc.} = 1D…
152 /* custom 4k entry 1D LUT */
154 …├─ "TYPE": immutable enum {1D enumerated curve, 1D LUT, 3x3 matrix, 3x4 matrix, 3D LUT, etc.} = 1D…
160 /* 17^3 3D LUT */
162 …├─ "TYPE": immutable enum {1D enumerated curve, 1D LUT, 3x3 matrix, 3x4 matrix, 3D LUT, etc.} = 3D…
266 ├─ "TYPE" (immutable) = 1D LUT
272 ├─ "TYPE" (immutable) = 3D LUT
/linux/drivers/clk/rockchip/
H A Dsoftrst.c15 const int *lut; member
31 if (softrst->lut) in rockchip_softrst_assert()
32 id = softrst->lut[id]; in rockchip_softrst_assert()
63 if (softrst->lut) in rockchip_softrst_deassert()
64 id = softrst->lut[id]; in rockchip_softrst_deassert()
106 softrst->lut = lookup_table; in rockchip_register_softrst_lut()
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_aal.c82 * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL
85 * Return: 0 if gamma control not supported in AAL or gamma LUT size
99 struct drm_color_lut *lut; in mtk_aal_gamma_set() local
107 /* Also, if there's no gamma lut there's nothing to do here. */ in mtk_aal_gamma_set()
111 lut = (struct drm_color_lut *)state->gamma_lut->data; in mtk_aal_gamma_set()
114 .red = drm_color_lut_extract(lut[i].red, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
115 .green = drm_color_lut_extract(lut[i].green, DISP_AAL_LUT_BITS), in mtk_aal_gamma_set()
116 .blue = drm_color_lut_extract(lut[i].blue, DISP_AAL_LUT_BITS) in mtk_aal_gamma_set()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dspp.h41 * struct dpu_hw_gc_lut - gc lut feature structure
44 * @c0: color0 component lut
45 * @c1: color1 component lut
46 * @c2: color2 component lut
71 * @gc_lut: Pointer to lut content
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_common.c259 * @lut: pointer to the lut buffer provided by the caller
260 * @lut_size: size of the lut buffer
267 u8 *lut, u16 lut_size, in iavf_aq_get_set_rss_lut() argument
301 status = iavf_asq_send_command(hw, &desc, lut, lut_size, NULL); in iavf_aq_get_set_rss_lut()
311 * @lut: pointer to the lut buffer provided by the caller
312 * @lut_size: size of the lut buffer
317 bool pf_lut, u8 *lut, u16 lut_size) in iavf_aq_set_rss_lut() argument
319 return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); in iavf_aq_set_rss_lut()
/linux/drivers/accel/amdxdna/
H A Daie2_error.c176 const struct aie_event_category *lut; in aie_get_error_category() local
182 lut = aie_ml_shim_tile_event_cat; in aie_get_error_category()
186 lut = aie_ml_core_event_cat; in aie_get_error_category()
191 lut = aie_ml_mem_tile_event_cat; in aie_get_error_category()
194 lut = aie_ml_mem_event_cat; in aie_get_error_category()
203 if (event_id != lut[i].event_id) in aie_get_error_category()
206 if (lut[i].category > AIE_ERROR_UNKNOWN) in aie_get_error_category()
209 return lut[i].category; in aie_get_error_category()
/linux/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c126 struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data; in malidp_generate_gamma_table() local
134 out_start = drm_color_lut_extract(lut[segments[i].start].green, in malidp_generate_gamma_table()
136 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12); in malidp_generate_gamma_table()
144 * Check if there is a new gamma LUT and if it is of an acceptable size. Also,
151 struct drm_color_lut *lut; in malidp_crtc_atomic_check_gamma() local
169 lut = (struct drm_color_lut *)state->gamma_lut->data; in malidp_crtc_atomic_check_gamma()
171 if (!((lut[i].red == lut[i].green) && in malidp_crtc_atomic_check_gamma()
172 (lut[i].red == lut[i].blue))) in malidp_crtc_atomic_check_gamma()
182 * changing the gamma LUT doesn't depend on any external in malidp_crtc_atomic_check_gamma()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c66 // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size) in dpp30_read_state()
555 ASSERT(0); // LUT select was updated again before vupdate in dpp3_deferred_update()
564 ASSERT(0); // LUT select was updated again before vupdate in dpp3_deferred_update()
573 ASSERT(0); // LUT select was updated again before vupdate in dpp3_deferred_update()
582 ASSERT(0); // LUT select was updated again before vupdate in dpp3_deferred_update()
714 /*program blnd lut RAM A*/
742 /*program blnd lut RAM B*/
1338 const struct dc_rgb *lut, in dpp3_set3dlut_ram12() argument
1345 red = lut[i].red<<4; in dpp3_set3dlut_ram12()
1346 green = lut[i].green<<4; in dpp3_set3dlut_ram12()
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/linux/drivers/hwmon/
H A Dmax31760.c47 } lut[LUT_SIZE]; member
491 struct lut_attribute *lut; in max31760_create_lut_nodes() local
494 lut = &state->lut[i]; in max31760_create_lut_nodes()
495 sda = &lut->sda; in max31760_create_lut_nodes()
497 snprintf(lut->name, sizeof(lut->name), in max31760_create_lut_nodes()
504 sda->dev_attr.attr.name = lut->name; in max31760_create_lut_nodes()

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