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/freebsd/sys/dev/flash/flexspi/
H A Dflex_spi.c195 uint32_t lut; in flex_spi_prepare_lut() local
197 /* unlock LUT */ in flex_spi_prepare_lut()
206 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_READ_IDENT); in flex_spi_prepare_lut()
207 lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0); in flex_spi_prepare_lut()
208 write_reg(sc, FSPI_LUT_REG(lut_id), lut); in flex_spi_prepare_lut()
212 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_FAST_READ); in flex_spi_prepare_lut()
213 lut |= LUT_DEF(1, LUT_ADDR, LUT_PAD(1), 3*8); in flex_spi_prepare_lut()
214 write_reg(sc, FSPI_LUT_REG(lut_id), lut); in flex_spi_prepare_lut()
215 lut = LUT_DEF(0, LUT_DUMMY, LUT_PAD(1), 1*8); in flex_spi_prepare_lut()
216 lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0); in flex_spi_prepare_lut()
[all …]
H A Dflex_spi.h246 /* Instruction set for the LUT register. */
276 /* LUT to operation mapping */
287 * Calculate number of required PAD bits for LUT register.
297 * Macro for constructing the LUT entries with the following
308 /* Macros for constructing the LUT register. */
/freebsd/sys/dev/netmap/
H A Dnetmap_mem2.c103 struct lut_entry *lut; /* virt,phys addresses, objtotal entries */ member
192 netmap_mem_get_lut(struct netmap_mem_d *nmd, struct netmap_lut *lut) in netmap_mem_get_lut() argument
197 rv = nmd->ops->nmd_get_lut(nmd, lut); in netmap_mem_get_lut()
504 netmap_mem2_get_lut(struct netmap_mem_d *nmd, struct netmap_lut *lut) in netmap_mem2_get_lut() argument
506 lut->lut = nmd->pools[NETMAP_BUF_POOL].lut; in netmap_mem2_get_lut()
508 lut->plut = lut->lut; in netmap_mem2_get_lut()
510 lut->objtotal = nmd->pools[NETMAP_BUF_POOL].objtotal; in netmap_mem2_get_lut()
511 lut->objsize = nmd->pools[NETMAP_BUF_POOL]._objsize; in netmap_mem2_get_lut()
769 struct lut_entry *lut; in nm_alloc_lut() local
771 lut = vmalloc(n); in nm_alloc_lut()
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,qcm2290-dpu.yaml33 - description: Display lut clock from dispcc
41 - const: lut
70 clock-names = "bus", "iface", "core", "lut", "vsync";
H A Dqcom,sm6115-dpu.yaml33 - description: Display lut
42 - const: lut
73 clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
H A Dqcom,sc7280-dpu.yaml33 - description: Display lut clock
42 - const: lut
77 "lut",
H A Dqcom,sc7180-dpu.yaml38 - description: Display lut clock
49 - const: lut
98 clock-names = "bus", "iface", "rot", "lut", "core",
H A Dqcom,sc8280xp-dpu.yaml36 - description: Display lut clock
45 - const: lut
74 "lut",
H A Dqcom,sm8350-dpu.yaml33 - description: Display lut clock
42 - const: lut
71 "lut",
H A Dqcom,sm8550-dpu.yaml33 - description: Display lut
42 - const: lut
77 "lut",
H A Dqcom,sm8450-dpu.yaml33 - description: Display lut
42 - const: lut
78 "lut",
H A Ddpu-qcm2290.yaml99 - description: Display lut clock from dispcc
107 - const: lut
201 clock-names = "bus", "iface", "core", "lut", "vsync";
H A Ddpu-sc7180.yaml98 - description: Display lut clock
107 - const: lut
207 clock-names = "bus", "iface", "rot", "lut", "core",
H A Ddpu-sc7280.yaml96 - description: Display lut clock
105 - const: lut
210 "lut",
/freebsd/sys/dev/iavf/
H A Diavf_common.c397 * @lut: pointer to the lut buffer provided by the caller
398 * @lut_size: size of the lut buffer
405 u8 *lut, u16 lut_size, in iavf_aq_get_set_rss_lut() argument
441 status = iavf_asq_send_command(hw, &desc, lut, lut_size, NULL); in iavf_aq_get_set_rss_lut()
451 * @lut: pointer to the lut buffer provided by the caller
452 * @lut_size: size of the lut buffer
457 bool pf_lut, u8 *lut, u16 lut_size) in iavf_aq_get_rss_lut() argument
459 return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, in iavf_aq_get_rss_lut()
468 * @lut: pointer to the lut buffer provided by the caller
469 * @lut_size: size of the lut buffer
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H A Diavf_prototype.h79 bool pf_lut, u8 *lut, u16 lut_size);
81 bool pf_lut, u8 *lut, u16 lut_size);
H A Diavf_lib.c485 "VSIs %d, QPs %d, MSI-X %d, RSS sizes: key %d lut %d\n", in iavf_print_device_info()
1078 u32 lut = 0; in iavf_config_rss_reg() local
1131 /* Populate the LUT with max no. of queues in round robin fashion */ in iavf_config_rss_reg()
1146 /* lut = 4-byte sliding window of 4 lut entries */ in iavf_config_rss_reg()
1147 lut = (lut << 8) | (que_id & IAVF_RSS_VF_LUT_ENTRY_MASK); in iavf_config_rss_reg()
1148 /* On i = 3, we have 4 entries in lut; write to the register */ in iavf_config_rss_reg()
1150 wr32(hw, IAVF_VFQF_HLUT(i >> 2), lut); in iavf_config_rss_reg()
1152 i, lut); in iavf_config_rss_reg()
H A Diavf_vc_common.c771 u32 lut; in iavf_config_rss_lut() local
779 device_printf(sc->dev, "Unable to allocate msg memory for RSS lut msg.\n"); in iavf_config_rss_lut()
784 /* Each LUT entry is a max of 1 byte, so this is easy */ in iavf_config_rss_lut()
787 /* Populate the LUT with max no. of queues in round robin fashion */ in iavf_config_rss_lut()
800 lut = que_id & IAVF_RSS_VSI_LUT_ENTRY_MASK; in iavf_config_rss_lut()
801 rss_lut_msg->lut[i] = lut; in iavf_config_rss_lut()
/freebsd/sys/contrib/device-tree/Bindings/display/rockchip/
H A Drockchip-vop2.yaml32 LUT address.
37 - const: gamma-lut
174 reg-names = "vop", "gamma-lut";
/freebsd/sys/dev/ixl/
H A Dixl_pf_iov.c1321 struct virtchnl_rss_lut *lut; in ixl_vf_config_rss_lut_msg() local
1326 lut = msg; in ixl_vf_config_rss_lut_msg()
1328 if (lut->lut_entries > 64) { in ixl_vf_config_rss_lut_msg()
1329 device_printf(pf->dev, "VF %d: # of LUT entries in msg (%d) is greater than max (%d)\n", in ixl_vf_config_rss_lut_msg()
1330 vf->vf_num, lut->lut_entries, 64); in ixl_vf_config_rss_lut_msg()
1336 if (lut->vsi_id != vf->vsi.vsi_num) { in ixl_vf_config_rss_lut_msg()
1338 vf->vf_num, lut->vsi_id, vf->vsi.vsi_num); in ixl_vf_config_rss_lut_msg()
1344 /* Fill out LUT using MAC-dependent method */ in ixl_vf_config_rss_lut_msg()
1346 status = i40e_aq_set_rss_lut(hw, vf->vsi.vsi_num, false, lut->lut, lut->lut_entries); in ixl_vf_config_rss_lut_msg()
1355 for (int i = 0; i < (lut->lut_entries / 4); i++) in ixl_vf_config_rss_lut_msg()
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/freebsd/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson8m2.dtsi19 /delete-node/ video-lut@20;
21 canvas: video-lut@48 {
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_plx.c86 u_int alut; /* A-LUT is enabled for NTx */
205 /* Make sure Virtual to Link A-LUT is disabled. */ in ntb_plx_init()
209 /* Enable all Link Interface LUT entries for peer. */ in ntb_plx_init()
217 * Enable Virtual Interface LUT entry 0 for 0:0.*. in ntb_plx_init()
344 * keeps LUT index (original bus/slot), function is passed through. in ntb_plx_attach()
352 /* Detect A-LUT enable and size. */ in ntb_plx_attach()
356 device_printf(dev, "%u A-LUT entries\n", 128 * sc->alut); in ntb_plx_attach()
420 device_printf(dev, "Can't split with disabled A-LUT\n"); in ntb_plx_attach()
669 * Translation address has to be aligned to the BAR size, but A-LUT in ntb_plx_mw_get_range()
683 * The chip has no limit registers, but A-LUT, when available, allows in ntb_plx_mw_get_range()
[all …]
/freebsd/share/man/man4/
H A Dntb_hw_plx.457 Lookup Table (A-LUT).
74 If Address Lookup Table (A-LUT) is enabled, BAR2 can be split into several
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_regs.h345 #define BWN_NPHY_BPHY_CTL2_LUT 0x001F /* LUT index */
414 #define BWN_NPHY_RFCTL_LUT_TRSW_LO1 BWN_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */
415 #define BWN_NPHY_RFCTL_LUT_TRSW_UP1 BWN_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */
416 #define BWN_NPHY_RFCTL_LUT_TRSW_LO2 BWN_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */
417 #define BWN_NPHY_RFCTL_LUT_TRSW_UP2 BWN_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */
418 #define BWN_NPHY_RFCTL_LUT_TRSW_LO3 BWN_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */
419 #define BWN_NPHY_RFCTL_LUT_TRSW_UP3 BWN_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */
420 #define BWN_NPHY_RFCTL_LUT_TRSW_LO4 BWN_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */
421 #define BWN_NPHY_RFCTL_LUT_TRSW_UP4 BWN_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */
422 #define BWN_NPHY_RFCTL_LUT_LNAPA1 BWN_PHY_N(0x100) /* RF control LUT LNA PA 1 */
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dcoex.h102 * @primary_ch_lut: LUT used for primary channel &enum iwl_bt_coex_lut_type
103 * @secondary_ch_lut: LUT used for secondary channel &enum iwl_bt_coex_lut_type

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