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Searched full:lrck (Results 1 – 25 of 77) sorted by relevance

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/linux/sound/soc/codecs/
H A Des8311.c43 "0.25db/4LRCK", \
44 "0.25db/8LRCK", \
45 "0.25db/16LRCK", \
46 "0.25db/32LRCK", \
47 "0.25db/64LRCK", \
48 "0.25db/128LRCK", \
49 "0.25db/256LRCK", \
50 "0.25db/512LRCK", \
51 "0.25db/1024LRCK", \
52 "0.25db/2048LRCK", \
[all …]
H A Dcs43130.h58 #define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /* ASP LRCK High Time 1 */
59 #define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /* ASP LRCK High Time 2 */
60 #define CS43130_ASP_LRCK_PERIOD_1 0x040016 /* ASP LRCK Period 1 */
61 #define CS43130_ASP_LRCK_PERIOD_2 0x040017 /* ASP LRCK Period 2 */
68 #define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /* XSP LRCK High Time 1 */
69 #define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /* XSP LRCK High Time 2 */
70 #define CS43130_XSP_LRCK_PERIOD_1 0x040026 /* XSP LRCK Period 1 */
71 #define CS43130_XSP_LRCK_PERIOD_2 0x040027 /* XSP LRCK Period 2 */
H A Des8326.c199 "0.25db/2 LRCK",
200 "0.25db/4 LRCK",
201 "0.25db/8 LRCK",
202 "0.25db/16 LRCK",
203 "0.25db/32 LRCK",
204 "0.25db/64 LRCK",
205 "0.25db/128 LRCK",
206 "0.25db/256 LRCK",
207 "0.25db/512 LRCK",
208 "0.25db/1024 LRCK",
[all …]
H A Drt1016.c222 SND_SOC_DAPM_SUPPLY("LRCK Det", RT1016_CLOCK_4, RT1016_PWR_LRCK_DET_BIT,
278 { "DAC", NULL, "LRCK Det" },
312 rt1016->lrck = params_rate(params); in rt1016_hw_params()
313 pre_div = rl6231_get_clk_info(rt1016->sysclk, rt1016->lrck); in rt1016_hw_params()
327 rt1016->bclk = rt1016->lrck * (32 << bclk_ms); in rt1016_hw_params()
333 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt1016_hw_params()
334 rt1016->lrck, pre_div, dai->id); in rt1016_hw_params()
H A Drt1019.c166 rt1019->lrck = params_rate(params); in rt1019_hw_params()
167 pre_div = rl6231_get_clk_info(rt1019->sysclk, rt1019->lrck); in rt1019_hw_params()
180 rt1019->bclk = rt1019->lrck * (32 << bclk_ms); in rt1019_hw_params()
182 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", in rt1019_hw_params()
183 rt1019->bclk, rt1019->lrck); in rt1019_hw_params()
H A Drt1308.c53 int lrck; member
459 rt1308->lrck = params_rate(params); in rt1308_hw_params()
460 pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck); in rt1308_hw_params()
463 "Unsupported clock setting %d\n", rt1308->lrck); in rt1308_hw_params()
475 rt1308->bclk = rt1308->lrck * (32 << bclk_ms); in rt1308_hw_params()
480 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt1308_hw_params()
481 rt1308->lrck, pre_div, dai->id); in rt1308_hw_params()
H A Drt1305.c76 int lrck; member
631 rt1305->lrck = params_rate(params); in rt1305_hw_params()
632 pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck); in rt1305_hw_params()
636 rt1305->lrck * 64, rt1305->lrck * 256); in rt1305_hw_params()
638 rt1305->lrck * 256, SND_SOC_CLOCK_IN); in rt1305_hw_params()
649 rt1305->bclk = rt1305->lrck * (32 << bclk_ms); in rt1305_hw_params()
654 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt1305_hw_params()
655 rt1305->lrck, pre_div, dai->id); in rt1305_hw_params()
H A Drt1015.c704 int pre_div, frame_size, lrck; in rt1015_hw_params() local
707 lrck = params_rate(params); in rt1015_hw_params()
708 pre_div = rl6231_get_clk_info(rt1015->sysclk, lrck); in rt1015_hw_params()
723 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt1015_hw_params()
724 lrck, pre_div, dai->id); in rt1015_hw_params()
H A Drt5616.c149 int lrck[RT5616_AIFS]; member
965 rt5616->lrck[dai->id] = params_rate(params); in rt5616_hw_params()
967 pre_div = rl6231_get_clk_info(rt5616->sysclk, rt5616->lrck[dai->id]); in rt5616_hw_params()
979 rt5616->bclk[dai->id] = rt5616->lrck[dai->id] * (32 << bclk_ms); in rt5616_hw_params()
981 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", in rt5616_hw_params()
982 rt5616->bclk[dai->id], rt5616->lrck[dai->id]); in rt5616_hw_params()
H A Drt5660.c841 rt5660->lrck[dai->id] = params_rate(params); in rt5660_hw_params()
842 pre_div = rl6231_get_clk_info(rt5660->sysclk, rt5660->lrck[dai->id]); in rt5660_hw_params()
845 rt5660->lrck[dai->id], dai->id); in rt5660_hw_params()
860 rt5660->bclk[dai->id] = rt5660->lrck[dai->id] * (32 << bclk_ms); in rt5660_hw_params()
862 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", in rt5660_hw_params()
863 rt5660->bclk[dai->id], rt5660->lrck[dai->id]); in rt5660_hw_params()
H A Drt5631.h367 /* 0:ADC data appear at left phase of LRCK
368 * 1:ADC data appear at right phase of LRCK
371 /* 0:DAC data appear at left phase of LRCK
372 * 1:DAC data appear at right phase of LRCK
H A Dcs53l30.h37 #define CS53L30_LRCK_CTL1 0x1B /* LRCK Control 1. */
38 #define CS53L30_LRCK_CTL2 0x1C /* LRCK Control 2. */
214 /* R28 (0x1C) CS53L30_LRCK_CTL2 - LRCK Control 2 */
H A Drt5682.c831 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
1296 ref = 256 * rt5682->lrck[RT5682_AIF2]; in set_filter_clk()
1298 ref = 256 * rt5682->lrck[RT5682_AIF1]; in set_filter_clk()
2140 rt5682->lrck[dai->id] = params_rate(params); in rt5682_hw_params()
2141 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); in rt5682_hw_params()
2150 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5682_hw_params()
2151 rt5682->lrck[dai->id], pre_div, dai->id); in rt5682_hw_params()
2668 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && in rt5682_wclk_recalc_rate()
2669 rt5682->lrck[RT5682_AIF1] != CLK_44) { in rt5682_wclk_recalc_rate()
2675 return rt5682->lrck[RT5682_AIF in rt5682_wclk_recalc_rate()
[all...]
H A Drt5682s.c1046 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can
1230 ref = 256 * rt5682s->lrck[RT5682S_AIF2]; in set_filter_clk()
1232 ref = 256 * rt5682s->lrck[RT5682S_AIF1]; in set_filter_clk()
1302 pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]); in rt5682s_set_i2s()
1308 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n", in rt5682s_set_i2s()
1309 rt5682s->lrck[id], pre_div, id); in rt5682s_set_i2s()
2068 rt5682s->lrck[dai->id] = params_rate(params); in rt5682s_hw_params()
2551 ref = 256 * rt5682s->lrck[RT5682S_AIF1]; in rt5682s_wclk_prepare()
2603 if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 && in rt5682s_wclk_recalc_rate()
2604 rt5682s->lrck[RT5682S_AIF1] != CLK_44) { in rt5682s_wclk_recalc_rate()
[all …]
H A Dcs4270.c204 /* The number of MCLK/LRCK ratios supported by the CS4270 */
331 /* Figure out which MCLK/LRCK ratio to use */ in cs4270_hw_params()
334 ratio = cs4270->mclk / rate; /* MCLK/LRCK ratio */ in cs4270_hw_params()
H A Drt1011.c1580 rt1011->lrck = params_rate(params); in rt1011_hw_params()
1581 pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck); in rt1011_hw_params()
1585 rt1011->lrck * 64, rt1011->lrck * 256); in rt1011_hw_params()
1587 rt1011->lrck * 256, SND_SOC_CLOCK_IN); in rt1011_hw_params()
1598 rt1011->bclk = rt1011->lrck * (32 << bclk_ms); in rt1011_hw_params()
1603 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt1011_hw_params()
1604 rt1011->lrck, pre_div, dai->id); in rt1011_hw_params()
H A Drt5668.c55 int lrck[RT5668_AIFS]; member
808 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can
1200 ref = 256 * rt5668->lrck[RT5668_AIF2]; in set_filter_clk()
1202 ref = 256 * rt5668->lrck[RT5668_AIF1]; in set_filter_clk()
1927 rt5668->lrck[dai->id] = params_rate(params); in rt5668_hw_params()
1928 pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]); in rt5668_hw_params()
1937 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5668_hw_params()
1938 rt5668->lrck[dai->id], pre_div, dai->id); in rt5668_hw_params()
/linux/Documentation/devicetree/bindings/sound/
H A Drockchip,i2s-tdm.yaml103 description: Use TX BCLK/LRCK for both TX and RX.
107 description: Use RX BCLK/LRCK for both TX and RX.
H A Dnuvoton,nau8325.yaml49 MCLK_SRC/LRCK of 256, 400 or 500, and needs to detect the BCLK
H A Dsnps,designware-i2s.yaml55 - const: lrck
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126-pinctrl.dtsi127 i2s0m0_lrck_tx: i2s0m0-lrck-tx {
132 i2s0m0_lrck_rx: i2s0m0-lrck-rx {
177 i2s0m1_lrck_tx: i2s0m1-lrck-tx {
182 i2s0m1_lrck_rx: i2s0m1-lrck-rx {
/linux/sound/pci/oxygen/
H A Doxygen_regs.h130 #define OXYGEN_I2S_RATE_MASK 0x0007 /* LRCK */
142 #define OXYGEN_I2S_MCLK_MASK 0x0030 /* MCLK/LRCK */
154 #define OXYGEN_I2S_BCLK_MASK 0x0600 /* BCLK/LRCK */
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-suniv-f1c100s.c43 SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
76 SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
175 SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */
289 SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
/linux/sound/soc/dwc/
H A Ddwc-i2s.c813 { .id = "lrck" }, in jh7110_i2s_crg_slave_init()
824 struct clk *lrck; in jh7110_i2s_crg_slave_init() local
842 lrck = clks[6].clk; in jh7110_i2s_crg_slave_init()
862 /* The sources of BCLK and LRCK are the external codec. */ in jh7110_i2s_crg_slave_init()
867 ret = clk_set_parent(lrck, lrck_ext); in jh7110_i2s_crg_slave_init()
/linux/sound/soc/sunxi/
H A Dsun8i-codec.c367 /* Use the AIF2 BCLK and LRCK for AIF3. */ in sun8i_codec_set_fmt()
415 case SND_SOC_DAIFMT_NB_IF: /* Inverted LRCK */ in sun8i_codec_set_fmt()
429 /* Inverted LRCK is not available in DSP mode. */ in sun8i_codec_set_fmt()
438 * share the same polarity for the LRCK signal when they mean in sun8i_codec_set_fmt()
607 /* LRCK divider (BCLK/LRCK ratio) */ in sun8i_codec_hw_params()
613 /* AIF2 and AIF3 share AIF2's BCLK and LRCK generation circuitry. */ in sun8i_codec_hw_params()

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